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37c2bc4397
* fix switch ports with modes other than 1000M/Full
* set 32-bit dma_coherent_mask to get PPE to work with 4 GiB of RAM
* sync driver for built-in 1GE PHY with MediaTek SDK sources
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 4ae2f43b3a)
124 lines
3.8 KiB
Diff
124 lines
3.8 KiB
Diff
From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 10 Oct 2023 21:06:43 +0200
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Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of
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ADMAv2 on MT7981 and MT7986
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ADMA is plagued by RX hangs which can't easily detected and happen upon
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receival of a corrupted package.
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Use QDMA just like on netsys v1 which is also still present and usable, and
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doesn't suffer from that problem.
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Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
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1 file changed, 23 insertions(+), 23 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -108,16 +108,16 @@ static const struct mtk_reg_map mt7986_r
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.tx_irq_mask = 0x461c,
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.tx_irq_status = 0x4618,
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.pdma = {
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- .rx_ptr = 0x6100,
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- .rx_cnt_cfg = 0x6104,
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- .pcrx_ptr = 0x6108,
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- .glo_cfg = 0x6204,
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- .rst_idx = 0x6208,
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- .delay_irq = 0x620c,
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- .irq_status = 0x6220,
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- .irq_mask = 0x6228,
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- .adma_rx_dbg0 = 0x6238,
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- .int_grp = 0x6250,
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+ .rx_ptr = 0x4100,
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+ .rx_cnt_cfg = 0x4104,
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+ .pcrx_ptr = 0x4108,
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+ .glo_cfg = 0x4204,
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+ .rst_idx = 0x4208,
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+ .delay_irq = 0x420c,
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+ .irq_status = 0x4220,
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+ .irq_mask = 0x4228,
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+ .adma_rx_dbg0 = 0x4238,
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+ .int_grp = 0x4250,
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},
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.qdma = {
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.qtx_cfg = 0x4400,
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@@ -1206,7 +1206,7 @@ static bool mtk_rx_get_desc(struct mtk_e
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rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
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rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
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rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
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- if (mtk_is_netsys_v2_or_greater(eth)) {
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+ if (mtk_is_netsys_v3_or_greater(eth)) {
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rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
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rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
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}
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@@ -2154,7 +2154,7 @@ static int mtk_poll_rx(struct napi_struc
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break;
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/* find out which mac the packet come from. values start at 1 */
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- if (mtk_is_netsys_v2_or_greater(eth)) {
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+ if (mtk_is_netsys_v3_or_greater(eth)) {
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u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
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switch (val) {
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@@ -2266,7 +2266,7 @@ static int mtk_poll_rx(struct napi_struc
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skb->dev = netdev;
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bytes += skb->len;
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- if (mtk_is_netsys_v2_or_greater(eth)) {
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+ if (mtk_is_netsys_v3_or_greater(eth)) {
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reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
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hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
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if (hash != MTK_RXD5_FOE_ENTRY)
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@@ -2807,7 +2807,7 @@ static int mtk_rx_alloc(struct mtk_eth *
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rxd->rxd3 = 0;
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rxd->rxd4 = 0;
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- if (mtk_is_netsys_v2_or_greater(eth)) {
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+ if (mtk_is_netsys_v3_or_greater(eth)) {
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rxd->rxd5 = 0;
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rxd->rxd6 = 0;
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rxd->rxd7 = 0;
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@@ -4010,7 +4010,7 @@ static int mtk_hw_init(struct mtk_eth *e
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else
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mtk_hw_reset(eth);
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- if (mtk_is_netsys_v2_or_greater(eth)) {
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+ if (mtk_is_netsys_v3_or_greater(eth)) {
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/* Set FE to PDMAv2 if necessary */
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val = mtk_r32(eth, MTK_FE_GLO_MISC);
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mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
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@@ -5296,11 +5296,11 @@ static const struct mtk_soc_data mt7981_
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.dma_len_offset = 8,
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},
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.rx = {
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- .desc_size = sizeof(struct mtk_rx_dma_v2),
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- .irq_done_mask = MTK_RX_DONE_INT_V2,
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+ .desc_size = sizeof(struct mtk_rx_dma),
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+ .irq_done_mask = MTK_RX_DONE_INT,
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.dma_l4_valid = RX_DMA_L4_VALID_V2,
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- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
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- .dma_len_offset = 8,
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+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
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+ .dma_len_offset = 16,
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},
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};
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@@ -5322,11 +5322,11 @@ static const struct mtk_soc_data mt7986_
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.dma_len_offset = 8,
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},
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.rx = {
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- .desc_size = sizeof(struct mtk_rx_dma_v2),
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- .irq_done_mask = MTK_RX_DONE_INT_V2,
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+ .desc_size = sizeof(struct mtk_rx_dma),
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+ .irq_done_mask = MTK_RX_DONE_INT,
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.dma_l4_valid = RX_DMA_L4_VALID_V2,
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- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
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- .dma_len_offset = 8,
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+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
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+ .dma_len_offset = 16,
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},
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};
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