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298 lines
6.9 KiB
C
298 lines
6.9 KiB
C
/*
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* Copyright (C) 2010 Broadcom
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* Copyright (C) 2012 Stephen Warren
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/delay.h>
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#include <linux/stringify.h>
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#include <linux/reset.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/utils.h>
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#define MHZ (1000 * 1000)
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struct clk_oxnas_pllb {
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struct clk_hw hw;
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struct device_node *devnode;
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struct reset_control *rstc;
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};
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#define to_clk_oxnas_pllb(_hw) container_of(_hw, struct clk_oxnas_pllb, hw)
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static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long fin = parent_rate;
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unsigned long pll0;
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unsigned long fbdiv, refdiv, outdiv;
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pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0);
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refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
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refdiv += 1;
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outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
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outdiv += 1;
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fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1);
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/* seems we will not be here when pll is bypassed, so ignore this
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* case */
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return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
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}
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static const char *pll_clk_parents[] = {
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"oscillator",
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};
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static struct clk_ops plla_ops = {
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.recalc_rate = plla_clk_recalc_rate,
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};
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static struct clk_init_data clk_plla_init = {
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.name = "plla",
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.ops = &plla_ops,
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.parent_names = pll_clk_parents,
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.num_parents = ARRAY_SIZE(pll_clk_parents),
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};
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static struct clk_hw plla_hw = {
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.init = &clk_plla_init,
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};
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static int pllb_clk_is_prepared(struct clk_hw *hw)
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{
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struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
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return !!pllb->rstc;
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}
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static int pllb_clk_prepare(struct clk_hw *hw)
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{
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struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
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pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
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return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
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}
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static void pllb_clk_unprepare(struct clk_hw *hw)
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{
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struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
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BUG_ON(IS_ERR(pllb->rstc));
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reset_control_put(pllb->rstc);
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pllb->rstc = NULL;
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}
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static int pllb_clk_enable(struct clk_hw *hw)
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{
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struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
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BUG_ON(IS_ERR(pllb->rstc));
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/* put PLL into bypass */
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oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
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wmb();
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udelay(10);
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reset_control_assert(pllb->rstc);
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udelay(10);
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/* set PLL B control information */
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writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
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SEC_CTRL_PLLB_CTRL0);
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reset_control_deassert(pllb->rstc);
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udelay(100);
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oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
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return 0;
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}
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static void pllb_clk_disable(struct clk_hw *hw)
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{
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struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
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BUG_ON(IS_ERR(pllb->rstc));
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/* put PLL into bypass */
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oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
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wmb();
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udelay(10);
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reset_control_assert(pllb->rstc);
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}
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static struct clk_ops pllb_ops = {
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.prepare = pllb_clk_prepare,
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.unprepare = pllb_clk_unprepare,
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.is_prepared = pllb_clk_is_prepared,
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.enable = pllb_clk_enable,
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.disable = pllb_clk_disable,
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};
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static struct clk_init_data clk_pllb_init = {
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.name = "pllb",
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.ops = &pllb_ops,
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.parent_names = pll_clk_parents,
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.num_parents = ARRAY_SIZE(pll_clk_parents),
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};
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/* standard gate clock */
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struct clk_std {
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struct clk_hw hw;
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signed char bit;
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};
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#define NUM_STD_CLKS 17
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#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
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static int std_clk_is_enabled(struct clk_hw *hw)
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{
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struct clk_std *std = to_stdclk(hw);
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return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit);
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}
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static int std_clk_enable(struct clk_hw *hw)
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{
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struct clk_std *std = to_stdclk(hw);
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writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL);
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return 0;
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}
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static void std_clk_disable(struct clk_hw *hw)
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{
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struct clk_std *std = to_stdclk(hw);
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writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL);
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}
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static struct clk_ops std_clk_ops = {
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.enable = std_clk_enable,
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.disable = std_clk_disable,
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.is_enabled = std_clk_is_enabled,
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};
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static const char *std_clk_parents[] = {
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"oscillator",
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};
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static const char *eth_parents[] = {
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"gmacclk",
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};
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#define DECLARE_STD_CLKP(__clk, __bit, __parent) \
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static struct clk_init_data clk_##__clk##_init = { \
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.name = __stringify(__clk), \
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.ops = &std_clk_ops, \
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.parent_names = __parent, \
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.num_parents = ARRAY_SIZE(__parent), \
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}; \
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\
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static struct clk_std clk_##__clk = { \
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.bit = __bit, \
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.hw = { \
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.init = &clk_##__clk##_init, \
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}, \
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}
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#define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \
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std_clk_parents)
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DECLARE_STD_CLK(leon, 0);
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DECLARE_STD_CLK(dma_sgdma, 1);
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DECLARE_STD_CLK(cipher, 2);
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DECLARE_STD_CLK(sd, 3);
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DECLARE_STD_CLK(sata, 4);
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DECLARE_STD_CLK(audio, 5);
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DECLARE_STD_CLK(usbmph, 6);
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DECLARE_STD_CLKP(etha, 7, eth_parents);
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DECLARE_STD_CLK(pciea, 8);
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DECLARE_STD_CLK(static, 9);
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DECLARE_STD_CLK(ethb, 10);
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DECLARE_STD_CLK(pcieb, 11);
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DECLARE_STD_CLK(ref600, 12);
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DECLARE_STD_CLK(usbdev, 13);
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struct clk_hw *std_clk_hw_tbl[] = {
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&clk_leon.hw,
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&clk_dma_sgdma.hw,
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&clk_cipher.hw,
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&clk_sd.hw,
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&clk_sata.hw,
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&clk_audio.hw,
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&clk_usbmph.hw,
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&clk_etha.hw,
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&clk_pciea.hw,
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&clk_static.hw,
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&clk_ethb.hw,
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&clk_pcieb.hw,
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&clk_ref600.hw,
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&clk_usbdev.hw,
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};
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struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)];
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static struct clk_onecell_data std_clk_data;
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void __init oxnas_init_stdclk(struct device_node *np)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) {
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std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]);
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BUG_ON(IS_ERR(std_clk_tbl[i]));
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}
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std_clk_data.clks = std_clk_tbl;
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std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl);
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of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data);
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}
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CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk);
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void __init oxnas_init_plla(struct device_node *np)
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{
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struct clk *clk;
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clk = clk_register(NULL, &plla_hw);
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BUG_ON(IS_ERR(clk));
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/* mark it as enabled */
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clk_prepare_enable(clk);
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
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void __init oxnas_init_pllb(struct device_node *np)
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{
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struct clk *clk;
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struct clk_oxnas_pllb *pllb;
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pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
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BUG_ON(!pllb);
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pllb->hw.init = &clk_pllb_init;
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pllb->devnode = np;
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pllb->rstc = NULL;
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clk = clk_register(NULL, &pllb->hw);
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BUG_ON(IS_ERR(clk));
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
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