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aed03d5d0f
* Refreshed patches. * Deleted 210-Revert-led-core-Fix-brightness-setting-when-setting-.patch (was accepted upstream) * Deleted 812-pci-dwc-fix-enumeration.patch (was accepted upstream) Compile and run tested on lantiq Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
125 lines
4.2 KiB
Diff
125 lines
4.2 KiB
Diff
From 2988239956fddb3fb808cfb50fa8d4e68b893f3d Mon Sep 17 00:00:00 2001
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From: Boris Brezillon <boris.brezillon@free-electrons.com>
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Date: Thu, 1 Dec 2016 22:00:19 +0100
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Subject: [PATCH] clk: bcm: Support rate change propagation on bcm2835 clocks
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Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set
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to a precise rate (in our case 108MHz). With the current implementation,
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where peripheral clocks are not allowed to forward rate change requests
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to their parents, it is impossible to match this requirement unless the
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bootloader has configured things correctly, or a specific rate has been
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assigned through the DT (with the assigned-clk-rates property).
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Add a new field to struct bcm2835_clock_data to specify which parent
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clocks accept rate change propagation, and support set rate propagation
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in bcm2835_clock_determine_rate().
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Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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(cherry picked from commit 155e8b3b0ee320ae866b97dd31eba8a1f080a772)
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---
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drivers/clk/bcm/clk-bcm2835.c | 67 ++++++++++++++++++++++++++++++++++++++++---
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1 file changed, 63 insertions(+), 4 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -436,6 +436,9 @@ struct bcm2835_clock_data {
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const char *const *parents;
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int num_mux_parents;
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+ /* Bitmap encoding which parents accept rate change propagation. */
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+ unsigned int set_rate_parent;
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+
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u32 ctl_reg;
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u32 div_reg;
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@@ -1021,10 +1024,60 @@ bcm2835_clk_is_pllc(struct clk_hw *hw)
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return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
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}
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+static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
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+ int parent_idx,
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+ unsigned long rate,
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+ u32 *div,
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+ unsigned long *prate)
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+{
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+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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+ struct bcm2835_cprman *cprman = clock->cprman;
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+ const struct bcm2835_clock_data *data = clock->data;
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+ unsigned long best_rate;
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+ u32 curdiv, mindiv, maxdiv;
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+ struct clk_hw *parent;
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+
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+ parent = clk_hw_get_parent_by_index(hw, parent_idx);
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+
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+ if (!(BIT(parent_idx) & data->set_rate_parent)) {
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+ *prate = clk_hw_get_rate(parent);
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+ *div = bcm2835_clock_choose_div(hw, rate, *prate, true);
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+
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+ return bcm2835_clock_rate_from_divisor(clock, *prate,
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+ *div);
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+ }
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+
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+ if (data->frac_bits)
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+ dev_warn(cprman->dev,
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+ "frac bits are not used when propagating rate change");
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+
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+ /* clamp to min divider of 2 if we're dealing with a mash clock */
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+ mindiv = data->is_mash_clock ? 2 : 1;
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+ maxdiv = BIT(data->int_bits) - 1;
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+
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+ /* TODO: Be smart, and only test a subset of the available divisors. */
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+ for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
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+ unsigned long tmp_rate;
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+
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+ tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
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+ tmp_rate /= curdiv;
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+ if (curdiv == mindiv ||
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+ (tmp_rate > best_rate && tmp_rate <= rate))
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+ best_rate = tmp_rate;
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+
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+ if (best_rate == rate)
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+ break;
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+ }
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+
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+ *div = curdiv << CM_DIV_FRAC_BITS;
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+ *prate = curdiv * best_rate;
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+
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+ return best_rate;
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+}
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+
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static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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- struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct clk_hw *parent, *best_parent = NULL;
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bool current_parent_is_pllc;
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unsigned long rate, best_rate = 0;
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@@ -1052,9 +1105,8 @@ static int bcm2835_clock_determine_rate(
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if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
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continue;
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- prate = clk_hw_get_rate(parent);
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- div = bcm2835_clock_choose_div(hw, req->rate, prate, true);
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- rate = bcm2835_clock_rate_from_divisor(clock, prate, div);
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+ rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
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+ &div, &prate);
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if (rate > best_rate && rate <= req->rate) {
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best_parent = parent;
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best_prate = prate;
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@@ -1275,6 +1327,13 @@ static struct clk_hw *bcm2835_register_c
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if ((cprman_read(cprman, data->ctl_reg) & CM_ENABLE) == 0)
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init.flags &= ~CLK_IS_CRITICAL;
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+ /*
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+ * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
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+ * rate changes on at least of the parents.
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+ */
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+ if (data->set_rate_parent)
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+ init.flags |= CLK_SET_RATE_PARENT;
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+
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if (data->is_vpu_clock) {
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init.ops = &bcm2835_vpu_clock_clk_ops;
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} else {
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