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2464a9a8a4
Refreshed all patches. Compile-tested on: x86_64, ath79, lantiq Runtime-tested on: x86_64, ath79 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
108 lines
3.7 KiB
Diff
108 lines
3.7 KiB
Diff
From 6adf87956ee1043e6bf0ef83fa0eec1e755c0d48 Mon Sep 17 00:00:00 2001
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From: Marc Kleine-Budde <mkl@pengutronix.de>
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Date: Fri, 1 Mar 2019 12:17:30 +0100
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Subject: [PATCH] can: flexcan: convert struct flexcan_priv::rx_mask{1,2} to
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rx_mask
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The flexcan IP core has up to 64 mailboxes, each one has a corresponding
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interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
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imask1 or imask2 registers.
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In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX
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interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of
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struct flexcan_priv for this.
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This patch merges the two u32 rx_mask1 and rx_mask2 to a single u64 rx_mask
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variable, which simplifies the code a bit.
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 30 +++++++++++++-----------------
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1 file changed, 13 insertions(+), 17 deletions(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -142,6 +142,7 @@
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#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
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#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
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#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
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+#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
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#define FLEXCAN_IFLAG2_MB(x) BIT((x) & 0x1f)
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#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
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#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
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@@ -277,9 +278,8 @@ struct flexcan_priv {
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u8 mb_size;
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u8 clk_src; /* clock source of CAN Protocol Engine */
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+ u64 rx_mask;
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u32 reg_ctrl_default;
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- u32 rx_mask1;
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- u32 rx_mask2;
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struct clk *clk_ipg;
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struct clk *clk_per;
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@@ -874,16 +874,15 @@ static struct sk_buff *flexcan_mailbox_r
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return skb;
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}
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-
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static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
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{
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struct flexcan_regs __iomem *regs = priv->regs;
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- u32 iflag1, iflag2;
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+ u64 iflag;
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- iflag2 = priv->read(®s->iflag2) & priv->rx_mask2;
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- iflag1 = priv->read(®s->iflag1) & priv->rx_mask1;
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+ iflag = (u64)priv->read(®s->iflag2) << 32 |
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+ priv->read(®s->iflag1);
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- return (u64)iflag2 << 32 | iflag1;
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+ return iflag & priv->rx_mask;
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}
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static irqreturn_t flexcan_irq(int irq, void *dev_id)
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@@ -1054,6 +1053,7 @@ static int flexcan_chip_start(struct net
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struct flexcan_priv *priv = netdev_priv(dev);
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struct flexcan_regs __iomem *regs = priv->regs;
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u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
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+ u64 reg_imask;
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int err, i;
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struct flexcan_mb __iomem *mb;
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@@ -1226,8 +1226,9 @@ static int flexcan_chip_start(struct net
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/* enable interrupts atomically */
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disable_irq(dev->irq);
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priv->write(priv->reg_ctrl_default, ®s->ctrl);
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- priv->write(priv->rx_mask1, ®s->imask1);
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- priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), ®s->imask2);
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+ reg_imask = priv->rx_mask | FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
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+ priv->write(upper_32_bits(reg_imask), ®s->imask2);
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+ priv->write(lower_32_bits(reg_imask), ®s->imask1);
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enable_irq(dev->irq);
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/* print chip status */
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@@ -1324,19 +1325,14 @@ static int flexcan_open(struct net_devic
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priv->offload.mailbox_read = flexcan_mailbox_read;
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
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- u64 imask;
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-
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priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
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priv->offload.mb_last = priv->mb_count - 2;
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- imask = GENMASK_ULL(priv->offload.mb_last,
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- priv->offload.mb_first);
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- priv->rx_mask1 = imask;
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- priv->rx_mask2 = imask >> 32;
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-
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+ priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
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+ priv->offload.mb_first);
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err = can_rx_offload_add_timestamp(dev, &priv->offload);
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} else {
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- priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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+ priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
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err = can_rx_offload_add_fifo(dev, &priv->offload,
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FLEXCAN_NAPI_WEIGHT);
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