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aa8ba5166e
Replace pending 730-net-phy-at803x-fix-feature-detection.patch with upstream version and move it to backport. Refresh other related patch while moving it. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
128 lines
4.6 KiB
Diff
128 lines
4.6 KiB
Diff
From 67999555ff42e91de7654488d9a7735bd9e84555 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Sun, 10 Oct 2021 00:46:18 +0200
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Subject: net: phy: at803x: better describe debug regs
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Give a name to known debug regs from Documentation instead of using
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unknown hex values.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/at803x.c | 30 +++++++++++++++---------------
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1 file changed, 15 insertions(+), 15 deletions(-)
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--- a/drivers/net/phy/at803x.c
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+++ b/drivers/net/phy/at803x.c
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@@ -86,12 +86,12 @@
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#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
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#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
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-#define AT803X_DEBUG_REG_0 0x00
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+#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
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#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
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#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
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#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
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-#define AT803X_DEBUG_REG_5 0x05
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+#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
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#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
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@@ -100,7 +100,7 @@
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#define AT803X_DEBUG_REG_3C 0x3C
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-#define AT803X_DEBUG_REG_3D 0x3D
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+#define AT803X_DEBUG_REG_GREEN 0x3D
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#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
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#define AT803X_DEBUG_REG_1F 0x1F
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@@ -274,25 +274,25 @@ static int at803x_read_page(struct phy_d
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static int at803x_enable_rx_delay(struct phy_device *phydev)
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{
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- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
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+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
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AT803X_DEBUG_RX_CLK_DLY_EN);
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}
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static int at803x_enable_tx_delay(struct phy_device *phydev)
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{
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- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
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+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
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AT803X_DEBUG_TX_CLK_DLY_EN);
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}
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static int at803x_disable_rx_delay(struct phy_device *phydev)
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{
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- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
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+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
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AT803X_DEBUG_RX_CLK_DLY_EN, 0);
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}
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static int at803x_disable_tx_delay(struct phy_device *phydev)
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{
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- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
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+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
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AT803X_DEBUG_TX_CLK_DLY_EN, 0);
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}
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@@ -1236,9 +1236,9 @@ static int qca83xx_config_init(struct ph
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switch (switch_revision) {
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case 1:
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/* For 100M waveform */
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- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea);
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
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/* Turn on Gigabit clock */
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- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0);
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
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break;
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case 2:
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@@ -1246,8 +1246,8 @@ static int qca83xx_config_init(struct ph
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fallthrough;
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case 4:
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phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
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- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860);
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- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46);
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
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+ at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
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at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
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break;
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}
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@@ -1258,7 +1258,7 @@ static int qca83xx_config_init(struct ph
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*/
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if (phydev->drv->phy_id == QCA8327_A_PHY_ID ||
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phydev->drv->phy_id == QCA8327_B_PHY_ID)
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- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
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QCA8327_DEBUG_MANU_CTRL_EN, 0);
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/* Following original QCA sourcecode set port to prefer master */
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@@ -1276,12 +1276,12 @@ static void qca83xx_link_change_notify(s
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/* Set DAC Amplitude adjustment to +6% for 100m on link running */
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if (phydev->state == PHY_RUNNING) {
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if (phydev->speed == SPEED_100)
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- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
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QCA8327_DEBUG_MANU_CTRL_EN,
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QCA8327_DEBUG_MANU_CTRL_EN);
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} else {
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/* Reset DAC Amplitude adjustment */
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- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
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QCA8327_DEBUG_MANU_CTRL_EN, 0);
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}
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}
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@@ -1328,7 +1328,7 @@ static int qca83xx_suspend(struct phy_de
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phy_modify(phydev, MII_BMCR, mask, 0);
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}
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- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D,
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
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AT803X_DEBUG_GATE_CLK_IN1000, 0);
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at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
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