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ada3c41acd
Change the name mt7620a_tplink_archer.dtsi to mt7620a_tplink_8m.dtsi because it will also be a base for TP-Link non-Archer routers. Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
99 lines
1.9 KiB
Plaintext
99 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/leds/common.h>
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#include "mt7620a_tplink_8m.dtsi"
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/ {
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compatible = "tplink,archer-c2-v1", "ralink,mt7620a-soc";
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model = "TP-Link Archer C2 v1";
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aliases {
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led-boot = &led_wps;
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led-failsafe = &led_wps;
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led-running = &led_wps;
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led-upgrade = &led_wps;
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};
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leds {
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compatible = "gpio-leds";
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lan {
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function = LED_FUNCTION_LAN;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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};
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usb {
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function = LED_FUNCTION_USB;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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trigger-sources = <&ohci_port1>, <&ehci_port1>;
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linux,default-trigger = "usbport";
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};
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led_wps: wps {
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function = LED_FUNCTION_WPS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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wan {
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function = LED_FUNCTION_WAN;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
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};
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wlan {
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function = LED_FUNCTION_WLAN;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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};
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rtl8367rb {
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compatible = "realtek,rtl8367b";
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cpu_port = <6>;
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realtek,extif1 = <1 0 1 1 1 1 1 1 2>;
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mii-bus = <&mdio0>;
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "uartf", "wled", "ephy", "spi refclk";
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function = "gpio";
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
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nvmem-cells = <&macaddr_rom_f100 0>;
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nvmem-cell-names = "mac-address";
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port@5 {
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status = "okay";
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mediatek,fixed-link = <1000 1 1 1>;
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phy-mode = "rgmii";
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};
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mdio0: mdio-bus {
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status = "okay";
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};
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};
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&wmac {
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nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 0>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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&wifi {
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nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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