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770a9c6787
All modifications made by update_kernel.sh/no manual intervention needed Run-tested: ipq806x (R7800), ath79 (Archer C7v5), x86/64 No dmesg regressions, everything appears functional Signed-off-by: John Audia <graysky@archlinux.us> [add run test from PR] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
73 lines
2.1 KiB
Diff
73 lines
2.1 KiB
Diff
From 0f5cf5dcc3ca4f8e610ebe1e62e3d3546b9d09ca Mon Sep 17 00:00:00 2001
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From: Yangbo Lu <yangbo.lu@nxp.com>
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Date: Mon, 16 Sep 2019 19:17:44 +0800
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Subject: [PATCH] mmc: sdhci-of-esdhc: poll ESDHC_FLUSH_ASYNC_FIFO bit until
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completion
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The ESDHC_FLUSH_ASYNC_FIFO bit which is set to flush asynchronous FIFO
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should be polled until it's auto cleared by hardware.
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/mmc/host/sdhci-of-esdhc.c | 35 ++++++++++++++++++++++++++++-------
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1 file changed, 28 insertions(+), 7 deletions(-)
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--- a/drivers/mmc/host/sdhci-of-esdhc.c
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+++ b/drivers/mmc/host/sdhci-of-esdhc.c
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@@ -592,6 +592,32 @@ static void esdhc_clock_enable(struct sd
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}
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}
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+static void esdhc_flush_async_fifo(struct sdhci_host *host)
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+{
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+ ktime_t timeout;
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+ u32 val;
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+
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+ val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
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+ val |= ESDHC_FLUSH_ASYNC_FIFO;
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+ sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
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+
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+ /* Wait max 20 ms */
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+ timeout = ktime_add_ms(ktime_get(), 20);
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+ while (1) {
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+ bool timedout = ktime_after(ktime_get(), timeout);
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+
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+ if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) &
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+ ESDHC_FLUSH_ASYNC_FIFO))
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+ break;
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+ if (timedout) {
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+ pr_err("%s: flushing asynchronous FIFO timeout.\n",
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+ mmc_hostname(host->mmc));
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+ break;
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+ }
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+ usleep_range(10, 20);
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+ }
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+}
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+
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static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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@@ -684,9 +710,7 @@ static void esdhc_of_set_clock(struct sd
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sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
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esdhc_clock_enable(host, false);
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- temp = sdhci_readl(host, ESDHC_DMA_SYSCTL);
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- temp |= ESDHC_FLUSH_ASYNC_FIFO;
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- sdhci_writel(host, temp, ESDHC_DMA_SYSCTL);
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+ esdhc_flush_async_fifo(host);
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}
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/* Wait max 20 ms */
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@@ -888,10 +912,7 @@ static void esdhc_tuning_block_enable(st
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u32 val;
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esdhc_clock_enable(host, false);
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-
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- val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
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- val |= ESDHC_FLUSH_ASYNC_FIFO;
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- sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
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+ esdhc_flush_async_fifo(host);
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val = sdhci_readl(host, ESDHC_TBCTL);
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if (enable)
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