mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 06:57:57 +00:00
4a281a7789
RISC-V is a new CPU architecture aimed to be fully free and open. This
target will add support for it, based on 5.15.
Supports running on:
- HiFive Unleashed - FU540, first generation
- HiFive Unmatched - FU740, current latest generation, PCIe
SD-card images are generated, where the partitions are required to have
specific type codes. As it is commonplace nowadays, OpenSBI is used as the
first stage, with U-boot following as the proper bootloader.
Specifications:
HiFive Unleashed:
- CPU: SiFive FU540 quad-core RISC-V (U54, RV64IMAFDC or RV64GC)
- Memory: 8Gb
- Ethernet: 1x 10/100/1000
- Console: via microUSB
HiFive Unmatched:
- CPU: SiFive FU740 quad-core RISC-V (U74, RV64IMAFDCB or RV64GCB)
- Memory: 16Gb
- Ethernet: 1x 10/100/1000
- USB: 4x USB 3.2
- PCIe: - 1x PCIe Gen3 x8
- 1x M.2 key M (PCIe x4)
- 1x M.2 Key E (PCIe x1 / USB2.0)
- Console: via microUSB
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
(cherry picked from commit a3469a90c4)
27 lines
789 B
Diff
27 lines
789 B
Diff
From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
|
|
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
|
|
Date: Mon, 13 Sep 2021 02:18:30 -0700
|
|
Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
|
|
|
|
Add gpio-poweroff node to allow powering off the system.
|
|
|
|
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
|
|
---
|
|
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
|
|
1 file changed, 6 insertions(+)
|
|
|
|
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
|
|
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
|
|
@@ -85,6 +85,11 @@
|
|
clock-frequency = <RTCCLK_FREQ>;
|
|
clock-output-names = "rtcclk";
|
|
};
|
|
+
|
|
+ gpio-poweroff {
|
|
+ compatible = "gpio-poweroff";
|
|
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
};
|
|
|
|
&uart0 {
|