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54 lines
1.9 KiB
Diff
54 lines
1.9 KiB
Diff
From 39ce22c870f4503bed5e451acfcab21eba3b6239 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 27 Jul 2014 09:49:07 +0100
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Subject: [PATCH 10/53] arch: mips: ralink: add spi1 clocks
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based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/mt7620.c | 1 +
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arch/mips/ralink/rt305x.c | 1 +
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arch/mips/ralink/rt3883.c | 1 +
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3 files changed, 3 insertions(+)
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diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
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index 33a7e42..0ba49a1 100644
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -427,6 +427,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000100.timer", periph_rate);
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ralink_clk_add("10000120.watchdog", periph_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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+ ralink_clk_add("10000b40.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
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index c40776a..eeb747a 100644
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -202,6 +202,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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+ ralink_clk_add("10000b40.spi", sys_rate);
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ralink_clk_add("10000100.timer", wdt_rate);
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ralink_clk_add("10000120.watchdog", wdt_rate);
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ralink_clk_add("10000500.uart", uart_rate);
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diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
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index 86a535c..26827bc 100644
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--- a/arch/mips/ralink/rt3883.c
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+++ b/arch/mips/ralink/rt3883.c
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@@ -109,6 +109,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000120.watchdog", sys_rate);
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ralink_clk_add("10000500.uart", 40000000);
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ralink_clk_add("10000b00.spi", sys_rate);
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+ ralink_clk_add("10000b40.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", 40000000);
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ralink_clk_add("10100000.ethernet", sys_rate);
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ralink_clk_add("10180000.wmac", 40000000);
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--
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1.7.10.4
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