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05b3adc0db
The clocks for SPI busses were named wrongly which resulted in the
spi-mt65xx driver not requesting them. This has apparently been
worked around by marking the clocks required for SPI0 which is used
for SPI-NOR and SPI-NAND flash chips as critical.
Fix the device tree for all 3 generic SPI host controllers and no
longer mark clocks as critical.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 2b173ab730)
66 lines
3.4 KiB
Diff
66 lines
3.4 KiB
Diff
From patchwork Fri Nov 1 03:19:39 2024
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X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
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X-Patchwork-Id: 13858671
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Return-Path:
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<linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
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Date: Fri, 1 Nov 2024 03:19:39 +0000
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From: Daniel Golle <daniel@makrotopia.org>
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To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org,
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linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Uwe
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=?iso-8859-1?q?Kleine-K=F6nig?= <u.kleine-koenig@baylibre.com>,
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Sam Shih <sam.shih@mediatek.com>, Frank Wunderlich <frank-w@public-files.de>,
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Daniel Golle <daniel@makrotopia.org>,
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AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
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Matthias Brugger <matthias.bgg@gmail.com>, Stephen Boyd <sboyd@kernel.org>,
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Michael Turquette <mturquette@baylibre.com>
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Subject: [PATCH] clk: mediatek: mt7988-infracfg: SPI0 clocks are not critical
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Message-ID: <ZyRIy22aS_Yjoavg@pidgin.makrotopia.org>
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SPI0 clocks have wrongly been marked as critical while, probably due
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to the SPI driver not requesting them. This can (and should) be addressed
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in device tree instead.
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Remove CLK_IS_CRITICAL flag from clocks related to SPI0.
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Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC")
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++----
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1 file changed, 2 insertions(+), 4 deletions(-)
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--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
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+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
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@@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[
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GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
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GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
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CLK_IS_CRITICAL),
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- GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
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- CLK_IS_CRITICAL),
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+ GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12),
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GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
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GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
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- GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
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- CLK_IS_CRITICAL),
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+ GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15),
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GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
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GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
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GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
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