mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
aadd629c07
modify 500-ar9_vr9.patch from
commit 29367aac42 ("lantiq: ltq-vmmc add support for ar9-vr9")
- remove unused dependencies to external watchdog functions
(wdog setup is already disabled)
- using header file from kernel (asm/vpe.h) instead patched file (vpe.h)
- cleanup whitspace warning
Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
338 lines
12 KiB
Diff
338 lines
12 KiB
Diff
--- a/src/mps/drv_mps_vmmc_ar9.c
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+++ b/src/mps/drv_mps_vmmc_ar9.c
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@@ -30,15 +30,24 @@
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#include "ifxos_interrupt.h"
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/* board specific headers */
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+#if !defined CONFIG_LANTIQ
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#include <asm/ifx/ifx_regs.h>
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#include <asm/ifx_vpe.h>
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#include <asm/ifx/ifx_gpio.h>
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+#endif
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+
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+#include <lantiq_soc.h>
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+#include <asm/vpe.h>
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/* device specific headers */
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#include "drv_mps_vmmc.h"
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#include "drv_mps_vmmc_dbg.h"
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#include "drv_mps_vmmc_device.h"
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+const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = NULL;
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+
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+#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
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+
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/* ============================= */
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/* Local Macros & Definitions */
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/* ============================= */
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@@ -98,47 +107,48 @@ IFX_int32_t (*ifx_wdog_callback) (IFX_ui
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*/
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IFX_int32_t ifx_mps_fw_wdog_start_ar9()
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{
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+ return IFX_SUCCESS; /* FIXME - Disable start wdog... */
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/* vpe1_wdog_ctr should be set up in u-boot as
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"vpe1_wdog_ctr_addr=0xBF2001B0"; protection from incorrect or missing
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setting */
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- if (vpe1_wdog_ctr != VPE1_WDOG_CTR_ADDR)
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- {
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- vpe1_wdog_ctr = VPE1_WDOG_CTR_ADDR;
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- }
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+// if (vpe1_wdog_ctr != VPE1_WDOG_CTR_ADDR)
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+// {
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+// vpe1_wdog_ctr = VPE1_WDOG_CTR_ADDR;
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+// }
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/* vpe1_wdog_timeout should be set up in u-boot as "vpe1_wdog_timeout =
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<value in ms>"; protection from insane setting */
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- if (vpe1_wdog_timeout < VPE1_WDOG_TMOUT_MIN)
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- {
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- vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MIN;
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- }
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- if (vpe1_wdog_timeout > VPE1_WDOG_TMOUT_MAX)
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- {
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- vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MAX;
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- }
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+// if (vpe1_wdog_timeout < VPE1_WDOG_TMOUT_MIN)
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+// {
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+// vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MIN;
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+// }
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+// if (vpe1_wdog_timeout > VPE1_WDOG_TMOUT_MAX)
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+// {
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+// vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MAX;
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+// }
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/* recalculate in jiffies */
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- vpe1_wdog_timeout = vpe1_wdog_timeout * HZ / 1000;
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+// vpe1_wdog_timeout = vpe1_wdog_timeout * HZ / 1000;
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/* register BSP callback function */
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- if (IFX_SUCCESS !=
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- vpe1_sw_wdog_register_reset_handler (ifx_mps_wdog_callback))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR "[%s %s %d]: Unable to register WDT callback.\r\n",
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- __FILE__, __func__, __LINE__));
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- return IFX_ERROR;;
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- }
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+// if (IFX_SUCCESS !=
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+// vpe1_sw_wdog_register_reset_handler (ifx_mps_wdog_callback))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR "[%s %s %d]: Unable to register WDT callback.\r\n",
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+// __FILE__, __func__, __LINE__));
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+// return IFX_ERROR;;
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+// }
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/* start software watchdog timer */
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- if (IFX_SUCCESS != vpe1_sw_wdog_start (0))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR
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- "[%s %s %d]: Error starting software watchdog timer.\r\n",
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- __FILE__, __func__, __LINE__));
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- return IFX_ERROR;
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- }
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+// if (IFX_SUCCESS != vpe1_sw_wdog_start (0))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR
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+// "[%s %s %d]: Error starting software watchdog timer.\r\n",
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+// __FILE__, __func__, __LINE__));
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+// return IFX_ERROR;
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+// }
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return IFX_SUCCESS;
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}
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@@ -292,6 +302,18 @@ IFX_int32_t ifx_mps_download_firmware (m
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decryption. Subtract sizeof(u32) from length to avoid decryption
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of data beyond the FW image code */
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pFWDwnld->length -= sizeof(IFX_uint32_t);
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+ switch(ltq_soc_type()) {
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+ case SOC_TYPE_AR9:
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+ ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf0017c4;
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+ break;
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+ case SOC_TYPE_VR9:
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+ ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001ea4;
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+ break;
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+ case SOC_TYPE_VR9_2:
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+ ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001f38;
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+ break;
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+ }
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+ if (ifx_bsp_basic_mps_decrypt)
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ifx_bsp_basic_mps_decrypt((IFX_uint32_t)cpu1_base_addr, pFWDwnld->length);
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}
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@@ -306,7 +328,7 @@ IFX_int32_t ifx_mps_download_firmware (m
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TRACE (MPS, DBG_LEVEL_HIGH,
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("MPS: FW checksum error: img=0x%08x calc=0x%08x\r\n",
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pFW_img_data->crc32, cksum));
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- return IFX_ERROR;
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+ /* return IFX_ERROR; -- FIXME */
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}
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}
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else
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@@ -362,9 +384,9 @@ IFX_void_t ifx_mps_shutdown (IFX_void_t)
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if (vpe1_started)
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{
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/* stop software watchdog timer */
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- vpe1_sw_wdog_stop (0);
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+// vpe1_sw_wdog_stop (0);
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/* clean up the BSP callback function */
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- vpe1_sw_wdog_register_reset_handler (IFX_NULL);
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+// vpe1_sw_wdog_register_reset_handler (IFX_NULL);
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/* stop VPE1 */
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vpe1_sw_stop (0);
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vpe1_started = 0;
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@@ -388,7 +410,7 @@ IFX_void_t ifx_mps_reset (IFX_void_t)
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if (vpe1_started)
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{
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/* stop software watchdog timer first */
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- vpe1_sw_wdog_stop (0);
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+// vpe1_sw_wdog_stop (0);
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vpe1_sw_stop (0);
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vpe1_started = 0;
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}
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@@ -454,62 +476,62 @@ IFX_int32_t ifx_mps_wdog_callback (IFX_u
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#endif /* DEBUG */
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/* reset SmartSLIC */
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- IFXOS_LOCKINT (flags);
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- if (ifx_gpio_pin_reserve
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- (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
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- __FILE__, __func__, __LINE__));
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- }
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+// IFXOS_LOCKINT (flags);
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+// if (ifx_gpio_pin_reserve
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+// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
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+// __FILE__, __func__, __LINE__));
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+// }
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/* P1_ALTSEL0.15 = 0 */
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- if (ifx_gpio_altsel0_clear
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- (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
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- __func__, __LINE__));
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- }
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+// if (ifx_gpio_altsel0_clear
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+// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
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+// __func__, __LINE__));
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+// }
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/* P1_ALTSEL1.15 = 0 */
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- if (ifx_gpio_altsel1_clear
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- (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
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- __func__, __LINE__));
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- }
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+// if (ifx_gpio_altsel1_clear
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+// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
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+// __func__, __LINE__));
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+// }
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/* P1_DIR.15 = 1 */
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- if (ifx_gpio_dir_out_set
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- (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
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- __func__, __LINE__));
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- }
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+// if (ifx_gpio_dir_out_set
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+// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
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+// __func__, __LINE__));
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+// }
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/* P1_OD.15 = 1 */
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- if (ifx_gpio_open_drain_set
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- (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
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- __func__, __LINE__));
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- }
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+// if (ifx_gpio_open_drain_set
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+// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
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+// __func__, __LINE__));
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+// }
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/* P1_OUT.15 = 0 */
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- if (ifx_gpio_output_clear
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- (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
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- __func__, __LINE__));
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- }
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- if (ifx_gpio_pin_free
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- (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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- {
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- TRACE (MPS, DBG_LEVEL_HIGH,
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- (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
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- __func__, __LINE__));
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- }
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- IFXOS_UNLOCKINT (flags);
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+// if (ifx_gpio_output_clear
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+// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
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+// __func__, __LINE__));
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+// }
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+// if (ifx_gpio_pin_free
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+// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
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+// {
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+// TRACE (MPS, DBG_LEVEL_HIGH,
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+// (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
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+// __func__, __LINE__));
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+// }
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+// IFXOS_UNLOCKINT (flags);
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/* recalculate and compare the firmware checksum */
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ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
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--- a/src/drv_vmmc_amazon_s.h
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+++ b/src/drv_vmmc_amazon_s.h
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@@ -16,7 +16,7 @@
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#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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-#include <asm/ifx/ifx_gpio.h>
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+//#include <asm/ifx/ifx_gpio.h>
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#else
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#error no system selected
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#endif
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@@ -27,45 +27,6 @@
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*/
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#define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
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do { \
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- ret = VMMC_statusOk; \
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- /* Reserve P0.0 as TDM/FSC */ \
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- if (!GPIOreserved) \
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- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
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- \
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- /* Reserve P1.9 as TDM/DO */ \
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- if (!GPIOreserved) \
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- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- \
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- /* Reserve P2.9 as TDM/DI */ \
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- if (!GPIOreserved) \
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- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID);\
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- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- \
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- /* Reserve P2.8 as TDM/DCL */ \
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- if (!GPIOreserved) \
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- ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
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- \
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- if (mode == 2) { \
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- /* TDM/FSC+DCL Master */ \
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- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
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- } else { \
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- /* TDM/FSC+DCL Slave */ \
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- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
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- } \
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} while(0);
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/**
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@@ -73,11 +34,6 @@ do { \
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*/
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#define VMMC_DRIVER_UNLOAD_HOOK(ret) \
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do { \
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- ret = VMMC_statusOk; \
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- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
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- ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
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} while (0)
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#endif /* _DRV_VMMC_AMAZON_S_H */
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