mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-26 00:41:17 +00:00
e4ce3109f2
The node pinctrl0 is already set up in the SOC DTSI files, but defined again as member of pinctrl in most of the device DTS(I) files. This patch removes this redundancy for the entire ramips target. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
165 lines
2.7 KiB
Plaintext
165 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
/dts-v1/;
|
|
|
|
#include "mt7621.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
compatible = "xzwifi,creativebox-v1", "mediatek,mt7621-soc";
|
|
model = "CreativeBox v1";
|
|
|
|
aliases {
|
|
led-boot = &led_sys;
|
|
led-failsafe = &led_sys;
|
|
led-running = &led_sys;
|
|
led-upgrade = &led_sys;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,115200";
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
power {
|
|
label = "creativebox-v1:blue:power";
|
|
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
|
|
default-state = "on";
|
|
};
|
|
|
|
led_sys: sys {
|
|
label = "creativebox-v1:blue:sys";
|
|
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
internet {
|
|
label = "creativebox-v1:blue:internet";
|
|
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wlan2g {
|
|
label = "creativebox-v1:blue:wlan2g";
|
|
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
|
linux,default-trigger = "phy0tpt";
|
|
};
|
|
|
|
wlan5g {
|
|
label = "creativebox-v1:blue:wlan5g";
|
|
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
|
|
linux,default-trigger = "phy1tpt";
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "reset";
|
|
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
|
|
gpio_export {
|
|
compatible = "gpio-export";
|
|
#size-cells = <0>;
|
|
|
|
power_usb2 {
|
|
gpio-export,name = "power_usb2";
|
|
gpio-export,output = <1>;
|
|
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
power_usb3 {
|
|
gpio-export,name = "power_usb3";
|
|
gpio-export,output = <1>;
|
|
gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
power_sata {
|
|
gpio-export,name = "power_sata";
|
|
gpio-export,output = <1>;
|
|
gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <40000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "u-boot";
|
|
reg = <0x0 0x30000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@30000 {
|
|
label = "u-boot-env";
|
|
reg = <0x30000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
factory: partition@40000 {
|
|
label = "factory";
|
|
reg = <0x40000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@50000 {
|
|
compatible = "denx,uimage";
|
|
label = "firmware";
|
|
reg = <0x50000 0x1fb0000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&sdhci {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0 {
|
|
wifi@0,0 {
|
|
compatible = "pci1400,7603";
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x0000>;
|
|
};
|
|
};
|
|
|
|
&pcie1 {
|
|
wifi@0,0 {
|
|
compatible = "pci14c3,7662";
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x8000>;
|
|
ieee80211-freq-limit = <5000000 6000000>;
|
|
};
|
|
};
|
|
|
|
ðernet {
|
|
mtd-mac-address = <&factory 0xe000>;
|
|
};
|
|
|
|
&state_default {
|
|
gpio {
|
|
ralink,group = "wdt", "rgmii2";
|
|
ralink,function = "gpio";
|
|
};
|
|
};
|