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c09eb08dad
Import pending patches to support the upcoming Filogic platforms. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
70 lines
2.3 KiB
Diff
70 lines
2.3 KiB
Diff
From 7f6c8bdfe020c45c398c01b417460e3319476606 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 29 Jul 2022 10:43:39 +0800
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Subject: [PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow
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bypassing searching clock parent of xtal clock
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The mtk clock framework in u-boot uses array index for searching clock
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parent (kernel uses strings for search), so we need to specify a special
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clock with ID=0 for CLK_XTAL in u-boot.
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In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
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mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
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expected.
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However for newer chips, they may have some clocks with ID=0 not
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representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
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called. Current logic will make entire clock driver not working.
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This patch adds a flag to indicate that whether a clock driver needs clocks
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with ID=0 to call mtk_topckgen_get_mux_rate.
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/clk/mediatek/clk-mtk.c | 5 ++++-
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drivers/clk/mediatek/clk-mtk.h | 6 ++++++
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2 files changed, 10 insertions(+), 1 deletion(-)
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--- a/drivers/clk/mediatek/clk-mtk.c
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+++ b/drivers/clk/mediatek/clk-mtk.c
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@@ -314,12 +314,15 @@ static ulong mtk_topckgen_get_mux_rate(s
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struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
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const struct mtk_composite *mux = &priv->tree->muxes[off];
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u32 index;
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+ u32 flag = 0;
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index = readl(priv->base + mux->mux_reg);
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index &= mux->mux_mask << mux->mux_shift;
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index = index >> mux->mux_shift;
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- if (mux->parent[index])
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+ if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
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+ flag = 1;
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+ if (mux->parent[index] > 0 || flag == 1)
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return mtk_clk_find_parent_rate(clk, mux->parent[index],
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NULL);
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--- a/drivers/clk/mediatek/clk-mtk.h
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+++ b/drivers/clk/mediatek/clk-mtk.h
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@@ -11,6 +11,11 @@
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#define CLK_XTAL 0
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#define MHZ (1000 * 1000)
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+/* flags in struct mtk_clk_tree */
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+
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+/* clk id == 0 doesn't mean it's xtal clk */
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+#define CLK_BYPASS_XTAL BIT(0)
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+
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#define HAVE_RST_BAR BIT(0)
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#define CLK_DOMAIN_SCPSYS BIT(0)
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#define CLK_MUX_SETCLR_UPD BIT(1)
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@@ -197,6 +202,7 @@ struct mtk_clk_tree {
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const struct mtk_fixed_clk *fclks;
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const struct mtk_fixed_factor *fdivs;
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const struct mtk_composite *muxes;
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+ u32 flags;
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};
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struct mtk_clk_priv {
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