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e0e74d8a2c
swig has been installed on the buildbots a while a ago and Petr Štetiar got a fix for the pylibfdt error. Use that and re-enable the builds for mt7620 and mt7621. Refresh patches while at it. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
105 lines
3.0 KiB
Diff
105 lines
3.0 KiB
Diff
From d7cfa1cb5602a1d936df36ee70869753835de28e Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 20 May 2022 11:21:51 +0800
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Subject: [PATCH 04/25] mips: add support for noncached_alloc()
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This patch adds support for noncached_alloc() which was only supported by
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ARM platform.
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Unlike the ARM platform, MMU is not used in u-boot for MIPS. Instead, KSEG
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is provided to access uncached memory. So most code of this patch is copied
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from cache.c of ARM platform, with only two differences:
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1. MMU is untouched in noncached_set_region()
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2. Address returned by noncached_alloc() is converted using KSEG1ADDR()
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Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/mips/include/asm/system.h | 20 ++++++++++++++++
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arch/mips/lib/cache.c | 43 ++++++++++++++++++++++++++++++++++
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2 files changed, 63 insertions(+)
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--- a/arch/mips/include/asm/system.h
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+++ b/arch/mips/include/asm/system.h
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@@ -282,4 +282,24 @@ static inline void instruction_hazard_ba
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: "=&r"(tmp));
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}
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+#ifdef CONFIG_SYS_NONCACHED_MEMORY
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+/* 1MB granularity */
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+#define MMU_SECTION_SHIFT 20
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+#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
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+
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+/**
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+ * noncached_init() - Initialize non-cached memory region
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+ *
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+ * Initialize non-cached memory area. This memory region will be typically
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+ * located right below the malloc() area and be accessed from KSEG1.
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+ *
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+ * It is called during the generic post-relocation init sequence.
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+ *
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+ * Return: 0 if OK
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+ */
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+int noncached_init(void);
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+
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+phys_addr_t noncached_alloc(size_t size, size_t align);
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+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
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+
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#endif /* _ASM_SYSTEM_H */
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--- a/arch/mips/lib/cache.c
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+++ b/arch/mips/lib/cache.c
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@@ -6,6 +6,7 @@
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#include <common.h>
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#include <cpu_func.h>
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+#include <malloc.h>
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#include <asm/cache.h>
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#include <asm/cacheops.h>
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#include <asm/cm.h>
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@@ -197,3 +198,45 @@ void dcache_disable(void)
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/* ensure the pipeline doesn't contain now-invalid instructions */
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instruction_hazard_barrier();
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}
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+
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+#ifdef CONFIG_SYS_NONCACHED_MEMORY
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+static unsigned long noncached_start;
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+static unsigned long noncached_end;
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+static unsigned long noncached_next;
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+
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+void noncached_set_region(void)
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+{
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+}
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+
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+int noncached_init(void)
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+{
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+ phys_addr_t start, end;
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+ size_t size;
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+
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+ /* If this calculation changes, update board_f.c:reserve_noncached() */
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+ end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
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+ size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
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+ start = end - size;
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+
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+ debug("mapping memory %pa-%pa non-cached\n", &start, &end);
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+
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+ noncached_start = start;
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+ noncached_end = end;
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+ noncached_next = start;
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+
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+ return 0;
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+}
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+
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+phys_addr_t noncached_alloc(size_t size, size_t align)
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+{
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+ phys_addr_t next = ALIGN(noncached_next, align);
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+
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+ if (next >= noncached_end || (noncached_end - next) < size)
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+ return 0;
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+
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+ debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
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+ noncached_next = next + size;
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+
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+ return CKSEG1ADDR(next);
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+}
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+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
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