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0e5d67d483
Backport kernel patches for LS1043A Rev1.1 support from upstream, patchwork, and SDK. And update to latest u-boot to support LS1043A Rev1.1. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
62 lines
2.1 KiB
Diff
62 lines
2.1 KiB
Diff
From b57dcab78fdc76a6c56c2df71518fb022429e244 Mon Sep 17 00:00:00 2001
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From: Minghuan Lian <Minghuan.Lian@nxp.com>
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Date: Wed, 6 Apr 2016 19:02:07 +0800
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Subject: [PATCH 02/13] ARM: dts: ls1021a: add SCFG MSI dts node
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Cherry-pick upstream patch.
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Add SCFG MSI dts node and add msi-parent property to PCIe dts node
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that points to the corresponding MSI node.
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
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index 38272d0..527f653 100644
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--- a/arch/arm/boot/dts/ls1021a.dtsi
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+++ b/arch/arm/boot/dts/ls1021a.dtsi
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@@ -119,6 +119,20 @@
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};
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+ msi1: msi-controller@1570e00 {
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+ compatible = "fsl,1s1021a-msi";
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+ reg = <0x0 0x1570e00 0x0 0x8>;
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+ msi-controller;
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+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ msi2: msi-controller@1570e08 {
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+ compatible = "fsl,1s1021a-msi";
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+ reg = <0x0 0x1570e08 0x0 0x8>;
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+ msi-controller;
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+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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ifc: ifc@1530000 {
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compatible = "fsl,ifc", "simple-bus";
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reg = <0x0 0x1530000 0x0 0x10000>;
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@@ -554,6 +568,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&msi1>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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@@ -576,6 +591,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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+ msi-parent = <&msi2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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--
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2.1.0.27.g96db324
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