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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
198 lines
5.0 KiB
Diff
198 lines
5.0 KiB
Diff
From f3195b45a3845fd3892ca932a9cc8e352942dbcd Mon Sep 17 00:00:00 2001
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From: Jack Zhu <jack.zhu@starfivetech.com>
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Date: Fri, 12 May 2023 18:28:39 +0800
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Subject: [PATCH 081/122] media: dt-bindings: Add JH7110 Camera Subsystem
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Add the bindings documentation for Starfive JH7110 Camera Subsystem
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which is used for handing image sensor data.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
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---
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.../bindings/media/starfive,jh7110-camss.yaml | 179 ++++++++++++++++++
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1 file changed, 179 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml
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@@ -0,0 +1,179 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/media/starfive,jh7110-camss.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Starfive SoC CAMSS ISP
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+
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+maintainers:
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+ - Jack Zhu <jack.zhu@starfivetech.com>
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+ - Changhuang Liang <changhuang.liang@starfivetech.com>
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+
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+description:
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+ The Starfive CAMSS ISP is a Camera interface for Starfive JH7110 SoC. It
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+ consists of a VIN controller (Video In Controller, a top-level control until)
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+ and an ISP.
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-camss
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+
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+ reg:
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+ maxItems: 2
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+
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+ reg-names:
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+ items:
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+ - const: syscon
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+ - const: isp
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+
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+ clocks:
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+ maxItems: 7
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+
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+ clock-names:
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+ items:
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+ - const: apb_func
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+ - const: wrapper_clk_c
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+ - const: dvp_inv
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+ - const: axiwr
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+ - const: mipi_rx0_pxl
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+ - const: ispcore_2x
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+ - const: isp_axi
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+
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+ resets:
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+ maxItems: 6
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+
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+ reset-names:
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+ items:
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+ - const: wrapper_p
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+ - const: wrapper_c
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+ - const: axird
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+ - const: axiwr
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+ - const: isp_top_n
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+ - const: isp_top_axi
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+
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+ power-domains:
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+ items:
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+ - description: JH7110 ISP Power Domain Switch Controller.
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+
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+ interrupts:
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+ maxItems: 4
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+
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+ ports:
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+ $ref: /schemas/graph.yaml#/properties/ports
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+
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+ properties:
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+ port@0:
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+ $ref: /schemas/graph.yaml#/$defs/port-base
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+ unevaluatedProperties: false
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+ description: Input port for receiving DVP data.
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+
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+ properties:
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+ endpoint:
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+ $ref: video-interfaces.yaml#
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+ unevaluatedProperties: false
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+
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+ properties:
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+ bus-type:
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+ enum: [5, 6]
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+
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+ bus-width:
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+ enum: [8, 10, 12]
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+
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+ data-shift:
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+ enum: [0, 2]
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+ default: 0
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+
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+ hsync-active:
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+ enum: [0, 1]
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+ default: 1
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+
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+ vsync-active:
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+ enum: [0, 1]
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+ default: 1
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+
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+ required:
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+ - bus-type
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+ - bus-width
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+
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+ port@1:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description: Input port for receiving CSI data.
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+
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+ required:
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+ - port@0
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+ - port@1
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+
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+required:
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+ - compatible
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+ - reg
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+ - reg-names
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+ - clocks
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+ - clock-names
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+ - resets
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+ - reset-names
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+ - power-domains
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+ - interrupts
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+ - ports
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ isp@19840000 {
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+ compatible = "starfive,jh7110-camss";
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+ reg = <0x19840000 0x10000>,
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+ <0x19870000 0x30000>;
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+ reg-names = "syscon", "isp";
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+ clocks = <&ispcrg 0>,
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+ <&ispcrg 13>,
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+ <&ispcrg 2>,
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+ <&ispcrg 12>,
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+ <&ispcrg 1>,
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+ <&syscrg 51>,
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+ <&syscrg 52>;
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+ clock-names = "apb_func",
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+ "wrapper_clk_c",
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+ "dvp_inv",
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+ "axiwr",
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+ "mipi_rx0_pxl",
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+ "ispcore_2x",
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+ "isp_axi";
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+ resets = <&ispcrg 0>,
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+ <&ispcrg 1>,
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+ <&ispcrg 10>,
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+ <&ispcrg 11>,
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+ <&syscrg 41>,
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+ <&syscrg 42>;
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+ reset-names = "wrapper_p",
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+ "wrapper_c",
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+ "axird",
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+ "axiwr",
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+ "isp_top_n",
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+ "isp_top_axi";
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+ power-domains = <&pwrc 5>;
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+ interrupts = <92>, <87>, <88>, <90>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ port@0 {
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+ reg = <0>;
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+ vin_from_sc2235: endpoint {
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+ remote-endpoint = <&sc2235_to_vin>;
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+ bus-width = <8>;
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+ data-shift = <2>;
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+ hsync-active = <1>;
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+ vsync-active = <0>;
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+ pclk-sample = <1>;
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ vin_from_csi2rx: endpoint {
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+ remote-endpoint = <&csi2rx_to_vin>;
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+ };
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+ };
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+ };
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+ };
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