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a158f9f405
CI reported that patches need to be refreshed, so lets refresh. Signed-off-by: Robert Marko <robimarko@gmail.com>
188 lines
5.8 KiB
Diff
188 lines
5.8 KiB
Diff
From 7c82049adb0460985dd6a1e5c9b6954d901247d2 Mon Sep 17 00:00:00 2001
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From: Samin Guo <samin.guo@starfivetech.com>
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Date: Fri, 3 Mar 2023 16:50:58 +0800
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Subject: [PATCH 044/122] net: stmmac: Add glue layer for StarFive JH7110 SoC
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This adds StarFive dwmac driver support on the StarFive JH7110 SoC.
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Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
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Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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---
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MAINTAINERS | 1 +
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drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++
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drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
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.../ethernet/stmicro/stmmac/dwmac-starfive.c | 123 ++++++++++++++++++
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4 files changed, 137 insertions(+)
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create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -19662,6 +19662,7 @@ M: Emil Renner Berthing <kernel@esmil.dk
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M: Samin Guo <samin.guo@starfivetech.com>
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S: Maintained
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F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
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+F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
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STARFIVE JH7110 PLL CLOCK DRIVER
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M: Xingyu Wu <xingyu.wu@starfivetech.com>
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--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
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+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
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@@ -165,6 +165,18 @@ config DWMAC_SOCFPGA
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for the stmmac device driver. This driver is used for
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arria5 and cyclone5 FPGA SoCs.
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+config DWMAC_STARFIVE
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+ tristate "StarFive dwmac support"
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+ depends on OF && (ARCH_STARFIVE || COMPILE_TEST)
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+ select MFD_SYSCON
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+ default m if ARCH_STARFIVE
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+ help
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+ Support for ethernet controllers on StarFive RISC-V SoCs
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+
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+ This selects the StarFive platform specific glue layer support for
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+ the stmmac device driver. This driver is used for StarFive JH7110
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+ ethernet controller.
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+
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config DWMAC_STI
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tristate "STi GMAC support"
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default ARCH_STI
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--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
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+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
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@@ -23,6 +23,7 @@ obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas
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obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o
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obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
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obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
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+obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o
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obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
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obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o
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obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
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--- /dev/null
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
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@@ -0,0 +1,123 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * StarFive DWMAC platform driver
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+ *
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+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
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+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
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+ *
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+ */
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+
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+#include <linux/mfd/syscon.h>
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+#include <linux/of_device.h>
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+#include <linux/regmap.h>
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+
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+#include "stmmac_platform.h"
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+
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+struct starfive_dwmac {
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+ struct device *dev;
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+ struct clk *clk_tx;
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+};
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+
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+static void starfive_dwmac_fix_mac_speed(void *priv, unsigned int speed)
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+{
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+ struct starfive_dwmac *dwmac = priv;
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+ unsigned long rate;
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+ int err;
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+
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+ rate = clk_get_rate(dwmac->clk_tx);
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+
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+ switch (speed) {
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+ case SPEED_1000:
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+ rate = 125000000;
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+ break;
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+ case SPEED_100:
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+ rate = 25000000;
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+ break;
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+ case SPEED_10:
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+ rate = 2500000;
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+ break;
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+ default:
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+ dev_err(dwmac->dev, "invalid speed %u\n", speed);
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+ break;
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+ }
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+
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+ err = clk_set_rate(dwmac->clk_tx, rate);
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+ if (err)
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+ dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
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+}
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+
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+static int starfive_dwmac_probe(struct platform_device *pdev)
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+{
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+ struct plat_stmmacenet_data *plat_dat;
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+ struct stmmac_resources stmmac_res;
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+ struct starfive_dwmac *dwmac;
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+ struct clk *clk_gtx;
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+ int err;
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+
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+ err = stmmac_get_platform_resources(pdev, &stmmac_res);
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+ if (err)
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+ return dev_err_probe(&pdev->dev, err,
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+ "failed to get resources\n");
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+
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+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
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+ if (IS_ERR(plat_dat))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat),
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+ "dt configuration failed\n");
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+
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+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
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+ if (!dwmac)
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+ return -ENOMEM;
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+
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+ dwmac->clk_tx = devm_clk_get_enabled(&pdev->dev, "tx");
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+ if (IS_ERR(dwmac->clk_tx))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_tx),
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+ "error getting tx clock\n");
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+
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+ clk_gtx = devm_clk_get_enabled(&pdev->dev, "gtx");
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+ if (IS_ERR(clk_gtx))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(clk_gtx),
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+ "error getting gtx clock\n");
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+
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+ /* Generally, the rgmii_tx clock is provided by the internal clock,
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+ * which needs to match the corresponding clock frequency according
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+ * to different speeds. If the rgmii_tx clock is provided by the
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+ * external rgmii_rxin, there is no need to configure the clock
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+ * internally, because rgmii_rxin will be adaptively adjusted.
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+ */
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+ if (!device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk"))
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+ plat_dat->fix_mac_speed = starfive_dwmac_fix_mac_speed;
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+
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+ dwmac->dev = &pdev->dev;
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+ plat_dat->bsp_priv = dwmac;
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+ plat_dat->dma_cfg->dche = true;
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+
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+ err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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+ if (err) {
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+ stmmac_remove_config_dt(pdev, plat_dat);
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+ return err;
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id starfive_dwmac_match[] = {
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+ { .compatible = "starfive,jh7110-dwmac" },
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+ { /* sentinel */ }
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+};
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+MODULE_DEVICE_TABLE(of, starfive_dwmac_match);
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+
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+static struct platform_driver starfive_dwmac_driver = {
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+ .probe = starfive_dwmac_probe,
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+ .remove = stmmac_pltfr_remove,
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+ .driver = {
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+ .name = "starfive-dwmac",
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+ .pm = &stmmac_pltfr_pm_ops,
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+ .of_match_table = starfive_dwmac_match,
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+ },
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+};
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+module_platform_driver(starfive_dwmac_driver);
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+
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+MODULE_LICENSE("GPL");
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+MODULE_DESCRIPTION("StarFive DWMAC platform driver");
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+MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
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+MODULE_AUTHOR("Samin Guo <samin.guo@starfivetech.com>");
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