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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
177 lines
4.7 KiB
Diff
177 lines
4.7 KiB
Diff
From 514cae455122c799638226f4358e8e6f5e155248 Mon Sep 17 00:00:00 2001
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From: Jianlong Huang <jianlong.huang@starfivetech.com>
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Date: Thu, 9 Feb 2023 22:37:00 +0800
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Subject: [PATCH 027/122] dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
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Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller.
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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---
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.../pinctrl/starfive,jh7110-aon-pinctrl.yaml | 124 ++++++++++++++++++
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.../pinctrl/starfive,jh7110-pinctrl.h | 22 ++++
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2 files changed, 146 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
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@@ -0,0 +1,124 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 AON Pin Controller
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+
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+description: |
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+ Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
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+
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+ Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3
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+ can be multiplexed and have configurable bias, drive strength,
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+ schmitt trigger etc.
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+ Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
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+
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+maintainers:
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+ - Jianlong Huang <jianlong.huang@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-aon-pinctrl
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+
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+ reg:
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+ maxItems: 1
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+
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+ resets:
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+ maxItems: 1
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+
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+ interrupts:
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+ maxItems: 1
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+
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+ interrupt-controller: true
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+
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+ '#interrupt-cells':
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+ const: 2
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+
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+ gpio-controller: true
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+
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+ '#gpio-cells':
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+ const: 2
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+
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+patternProperties:
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+ '-[0-9]+$':
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+ type: object
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+ additionalProperties: false
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+ patternProperties:
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+ '-pins$':
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+ type: object
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+ description: |
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+ A pinctrl node should contain at least one subnode representing the
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+ pinctrl groups available on the machine. Each subnode will list the
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+ pins it needs, and how they should be configured, with regard to
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+ muxer configuration, bias, input enable/disable, input schmitt
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+ trigger enable/disable, slew-rate and drive strength.
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+ allOf:
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+ - $ref: /schemas/pinctrl/pincfg-node.yaml
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+ - $ref: /schemas/pinctrl/pinmux-node.yaml
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+ additionalProperties: false
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+
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+ properties:
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+ pinmux:
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+ description: |
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+ The list of GPIOs and their mux settings that properties in the
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+ node apply to. This should be set using the GPIOMUX macro.
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+
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+ bias-disable: true
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+
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+ bias-pull-up:
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+ type: boolean
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+
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+ bias-pull-down:
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+ type: boolean
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+
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+ drive-strength:
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+ enum: [ 2, 4, 8, 12 ]
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+
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+ input-enable: true
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+
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+ input-disable: true
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+
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+ input-schmitt-enable: true
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+
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+ input-schmitt-disable: true
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+
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+ slew-rate:
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+ maximum: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - interrupts
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+ - interrupt-controller
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+ - '#interrupt-cells'
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+ - gpio-controller
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+ - '#gpio-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ pinctrl@17020000 {
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+ compatible = "starfive,jh7110-aon-pinctrl";
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+ reg = <0x17020000 0x10000>;
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+ resets = <&aoncrg 2>;
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+ interrupts = <85>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ pwm-0 {
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+ pwm-pins {
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+ pinmux = <0xff030802>;
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+ bias-disable;
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+ drive-strength = <12>;
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+ input-disable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+ };
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+ };
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+
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+...
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--- a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
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+++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
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@@ -104,6 +104,28 @@
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#define PAD_QSPI_DATA2 93
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#define PAD_QSPI_DATA3 94
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+/* aon_iomux pins */
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+#define PAD_TESTEN 0
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+#define PAD_RGPIO0 1
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+#define PAD_RGPIO1 2
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+#define PAD_RGPIO2 3
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+#define PAD_RGPIO3 4
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+#define PAD_RSTN 5
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+#define PAD_GMAC0_MDC 6
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+#define PAD_GMAC0_MDIO 7
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+#define PAD_GMAC0_RXD0 8
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+#define PAD_GMAC0_RXD1 9
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+#define PAD_GMAC0_RXD2 10
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+#define PAD_GMAC0_RXD3 11
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+#define PAD_GMAC0_RXDV 12
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+#define PAD_GMAC0_RXC 13
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+#define PAD_GMAC0_TXD0 14
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+#define PAD_GMAC0_TXD1 15
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+#define PAD_GMAC0_TXD2 16
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+#define PAD_GMAC0_TXD3 17
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+#define PAD_GMAC0_TXEN 18
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+#define PAD_GMAC0_TXC 19
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+
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#define GPOUT_LOW 0
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#define GPOUT_HIGH 1
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