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https://github.com/openwrt/openwrt.git
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8a9273d51e
Copy backport, hack, pending patch and config from 6.1 to 6.6. Signed-off-by: Weijie Gao <hackpascal@gmail.com>
433 lines
16 KiB
Diff
433 lines
16 KiB
Diff
From: Sujuan Chen <sujuan.chen@mediatek.com>
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Date: Mon, 18 Sep 2023 12:29:18 +0200
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Subject: [PATCH] net: ethernet: mtk_wed: debugfs: add WED 3.0 debugfs entries
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Introduce WED3.0 debugfs entries useful for debugging.
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Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
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+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
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@@ -11,6 +11,7 @@ struct reg_dump {
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u16 offset;
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u8 type;
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u8 base;
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+ u32 mask;
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};
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enum {
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@@ -25,6 +26,8 @@ enum {
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#define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }
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#define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ }
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+#define DUMP_REG_MASK(_reg, _mask) \
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+ { #_mask, MTK_##_reg, DUMP_TYPE_WED, 0, MTK_##_mask }
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#define DUMP_RING(_prefix, _base, ...) \
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{ _prefix " BASE", _base, __VA_ARGS__ }, \
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{ _prefix " CNT", _base + 0x4, __VA_ARGS__ }, \
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@@ -32,6 +35,7 @@ enum {
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{ _prefix " DIDX", _base + 0xc, __VA_ARGS__ }
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#define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)
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+#define DUMP_WED_MASK(_reg, _mask) DUMP_REG_MASK(_reg, _mask)
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#define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED)
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#define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)
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@@ -212,12 +216,58 @@ wed_rxinfo_show(struct seq_file *s, void
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DUMP_WED(WED_RTQM_Q2B_MIB),
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DUMP_WED(WED_RTQM_PFDBK_MIB),
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};
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+ static const struct reg_dump regs_wed_v3[] = {
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+ DUMP_STR("WED RX RRO DATA"),
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+ DUMP_WED_RING(WED_RRO_RX_D_RX(0)),
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+ DUMP_WED_RING(WED_RRO_RX_D_RX(1)),
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+
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+ DUMP_STR("WED RX MSDU PAGE"),
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+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(0)),
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+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(1)),
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+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(2)),
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+
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+ DUMP_STR("WED RX IND CMD"),
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+ DUMP_WED(WED_IND_CMD_RX_CTRL1),
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+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL2, WED_IND_CMD_MAX_CNT),
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+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_PROC_IDX),
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+ DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_DMA_IDX),
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+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_MAGIC_CNT),
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+ DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_MAGIC_CNT),
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+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0,
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+ WED_IND_CMD_PREFETCH_FREE_CNT),
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+ DUMP_WED_MASK(WED_RRO_CFG1, WED_RRO_CFG1_PARTICL_SE_ID),
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+
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+ DUMP_STR("WED ADDR ELEM"),
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+ DUMP_WED(WED_ADDR_ELEM_CFG0),
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+ DUMP_WED_MASK(WED_ADDR_ELEM_CFG1,
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+ WED_ADDR_ELEM_PREFETCH_FREE_CNT),
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+
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+ DUMP_STR("WED Route QM"),
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+ DUMP_WED(WED_RTQM_ENQ_I2Q_DMAD_CNT),
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+ DUMP_WED(WED_RTQM_ENQ_I2N_DMAD_CNT),
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+ DUMP_WED(WED_RTQM_ENQ_I2Q_PKT_CNT),
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+ DUMP_WED(WED_RTQM_ENQ_I2N_PKT_CNT),
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+ DUMP_WED(WED_RTQM_ENQ_USED_ENTRY_CNT),
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+ DUMP_WED(WED_RTQM_ENQ_ERR_CNT),
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+
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+ DUMP_WED(WED_RTQM_DEQ_DMAD_CNT),
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+ DUMP_WED(WED_RTQM_DEQ_Q2I_DMAD_CNT),
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+ DUMP_WED(WED_RTQM_DEQ_PKT_CNT),
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+ DUMP_WED(WED_RTQM_DEQ_Q2I_PKT_CNT),
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+ DUMP_WED(WED_RTQM_DEQ_USED_PFDBK_CNT),
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+ DUMP_WED(WED_RTQM_DEQ_ERR_CNT),
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+ };
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struct mtk_wed_hw *hw = s->private;
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struct mtk_wed_device *dev = hw->wed_dev;
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if (dev) {
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dump_wed_regs(s, dev, regs_common, ARRAY_SIZE(regs_common));
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- dump_wed_regs(s, dev, regs_wed_v2, ARRAY_SIZE(regs_wed_v2));
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+ if (mtk_wed_is_v2(hw))
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+ dump_wed_regs(s, dev,
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+ regs_wed_v2, ARRAY_SIZE(regs_wed_v2));
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+ else
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+ dump_wed_regs(s, dev,
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+ regs_wed_v3, ARRAY_SIZE(regs_wed_v3));
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}
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return 0;
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@@ -225,6 +275,314 @@ wed_rxinfo_show(struct seq_file *s, void
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DEFINE_SHOW_ATTRIBUTE(wed_rxinfo);
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static int
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+wed_amsdu_show(struct seq_file *s, void *data)
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+{
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+ static const struct reg_dump regs[] = {
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+ DUMP_STR("WED AMDSU INFO"),
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+ DUMP_WED(WED_MON_AMSDU_FIFO_DMAD),
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+
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+ DUMP_STR("WED AMDSU ENG0 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(0)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(0)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(0)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(0)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(0)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(0),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(0),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED AMDSU ENG1 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(1)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(1)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(1)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(1)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(1)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(1),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(1),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(1),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED AMDSU ENG2 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(2)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(2)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(2)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(2)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(2)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(2),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(2),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED AMDSU ENG3 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(3)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(3)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(3)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(3)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(3)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(3),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(3),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED AMDSU ENG4 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(4)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(4)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(4)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(4)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(4)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(4),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(4),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED AMDSU ENG5 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(5)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(5)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(5)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(5)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(5)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(5),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(5),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED AMDSU ENG6 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(6)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(6)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(6)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(6)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(6)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(6),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(6),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED AMDSU ENG7 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(7)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(7)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(7)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(7)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(7)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(7),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(7),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(7),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(7),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED AMDSU ENG8 INFO"),
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+ DUMP_WED(WED_MON_AMSDU_ENG_DMAD(8)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QFPL(8)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENI(8)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_QENO(8)),
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+ DUMP_WED(WED_MON_AMSDU_ENG_MERG(8)),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(8),
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+ WED_AMSDU_ENG_MAX_PL_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(8),
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+ WED_AMSDU_ENG_MAX_QGPP_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
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+ WED_AMSDU_ENG_CUR_ENTRY),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
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+ WED_AMSDU_ENG_MAX_BUF_MERGED),
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+ DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
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+ WED_AMSDU_ENG_MAX_MSDU_MERGED),
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+
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+ DUMP_STR("WED QMEM INFO"),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(0), WED_AMSDU_QMEM_FQ_CNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(0), WED_AMSDU_QMEM_SP_QCNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(1), WED_AMSDU_QMEM_TID0_QCNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(1), WED_AMSDU_QMEM_TID1_QCNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(2), WED_AMSDU_QMEM_TID2_QCNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(2), WED_AMSDU_QMEM_TID3_QCNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(3), WED_AMSDU_QMEM_TID4_QCNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(3), WED_AMSDU_QMEM_TID5_QCNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(4), WED_AMSDU_QMEM_TID6_QCNT),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(4), WED_AMSDU_QMEM_TID7_QCNT),
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+
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+ DUMP_STR("WED QMEM HEAD INFO"),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(0), WED_AMSDU_QMEM_FQ_HEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(0), WED_AMSDU_QMEM_SP_QHEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(1), WED_AMSDU_QMEM_TID0_QHEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(1), WED_AMSDU_QMEM_TID1_QHEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(2), WED_AMSDU_QMEM_TID2_QHEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(2), WED_AMSDU_QMEM_TID3_QHEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(3), WED_AMSDU_QMEM_TID4_QHEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(3), WED_AMSDU_QMEM_TID5_QHEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(4), WED_AMSDU_QMEM_TID6_QHEAD),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(4), WED_AMSDU_QMEM_TID7_QHEAD),
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+
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+ DUMP_STR("WED QMEM TAIL INFO"),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(5), WED_AMSDU_QMEM_FQ_TAIL),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(5), WED_AMSDU_QMEM_SP_QTAIL),
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+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(6), WED_AMSDU_QMEM_TID0_QTAIL),
|
|
+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(6), WED_AMSDU_QMEM_TID1_QTAIL),
|
|
+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(7), WED_AMSDU_QMEM_TID2_QTAIL),
|
|
+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(7), WED_AMSDU_QMEM_TID3_QTAIL),
|
|
+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(8), WED_AMSDU_QMEM_TID4_QTAIL),
|
|
+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(8), WED_AMSDU_QMEM_TID5_QTAIL),
|
|
+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(9), WED_AMSDU_QMEM_TID6_QTAIL),
|
|
+ DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(9), WED_AMSDU_QMEM_TID7_QTAIL),
|
|
+
|
|
+ DUMP_STR("WED HIFTXD MSDU INFO"),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(1)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(2)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(3)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(4)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(5)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(6)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(7)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(8)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(9)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(10)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(11)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(12)),
|
|
+ DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(13)),
|
|
+ };
|
|
+ struct mtk_wed_hw *hw = s->private;
|
|
+ struct mtk_wed_device *dev = hw->wed_dev;
|
|
+
|
|
+ if (dev)
|
|
+ dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+DEFINE_SHOW_ATTRIBUTE(wed_amsdu);
|
|
+
|
|
+static int
|
|
+wed_rtqm_show(struct seq_file *s, void *data)
|
|
+{
|
|
+ static const struct reg_dump regs[] = {
|
|
+ DUMP_STR("WED Route QM IGRS0(N2H + Recycle)"),
|
|
+ DUMP_WED(WED_RTQM_IGRS0_I2HW_DMAD_CNT),
|
|
+ DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(1)),
|
|
+ DUMP_WED(WED_RTQM_IGRS0_I2HW_PKT_CNT),
|
|
+ DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS0_FDROP_CNT),
|
|
+
|
|
+ DUMP_STR("WED Route QM IGRS1(Legacy)"),
|
|
+ DUMP_WED(WED_RTQM_IGRS1_I2HW_DMAD_CNT),
|
|
+ DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(1)),
|
|
+ DUMP_WED(WED_RTQM_IGRS1_I2HW_PKT_CNT),
|
|
+ DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(1)),
|
|
+ DUMP_WED(WED_RTQM_IGRS1_FDROP_CNT),
|
|
+
|
|
+ DUMP_STR("WED Route QM IGRS2(RRO3.0)"),
|
|
+ DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
|
|
+ DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(1)),
|
|
+ DUMP_WED(WED_RTQM_IGRS2_I2HW_PKT_CNT),
|
|
+ DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(1)),
|
|
+ DUMP_WED(WED_RTQM_IGRS2_FDROP_CNT),
|
|
+
|
|
+ DUMP_STR("WED Route QM IGRS3(DEBUG)"),
|
|
+ DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
|
|
+ DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(1)),
|
|
+ DUMP_WED(WED_RTQM_IGRS3_I2HW_PKT_CNT),
|
|
+ DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(0)),
|
|
+ DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(1)),
|
|
+ DUMP_WED(WED_RTQM_IGRS3_FDROP_CNT),
|
|
+ };
|
|
+ struct mtk_wed_hw *hw = s->private;
|
|
+ struct mtk_wed_device *dev = hw->wed_dev;
|
|
+
|
|
+ if (dev)
|
|
+ dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+DEFINE_SHOW_ATTRIBUTE(wed_rtqm);
|
|
+
|
|
+static int
|
|
+wed_rro_show(struct seq_file *s, void *data)
|
|
+{
|
|
+ static const struct reg_dump regs[] = {
|
|
+ DUMP_STR("RRO/IND CMD CNT"),
|
|
+ DUMP_WED(WED_RX_IND_CMD_CNT(1)),
|
|
+ DUMP_WED(WED_RX_IND_CMD_CNT(2)),
|
|
+ DUMP_WED(WED_RX_IND_CMD_CNT(3)),
|
|
+ DUMP_WED(WED_RX_IND_CMD_CNT(4)),
|
|
+ DUMP_WED(WED_RX_IND_CMD_CNT(5)),
|
|
+ DUMP_WED(WED_RX_IND_CMD_CNT(6)),
|
|
+ DUMP_WED(WED_RX_IND_CMD_CNT(7)),
|
|
+ DUMP_WED(WED_RX_IND_CMD_CNT(8)),
|
|
+ DUMP_WED_MASK(WED_RX_IND_CMD_CNT(9),
|
|
+ WED_IND_CMD_MAGIC_CNT_FAIL_CNT),
|
|
+
|
|
+ DUMP_WED(WED_RX_ADDR_ELEM_CNT(0)),
|
|
+ DUMP_WED_MASK(WED_RX_ADDR_ELEM_CNT(1),
|
|
+ WED_ADDR_ELEM_SIG_FAIL_CNT),
|
|
+ DUMP_WED(WED_RX_MSDU_PG_CNT(1)),
|
|
+ DUMP_WED(WED_RX_MSDU_PG_CNT(2)),
|
|
+ DUMP_WED(WED_RX_MSDU_PG_CNT(3)),
|
|
+ DUMP_WED(WED_RX_MSDU_PG_CNT(4)),
|
|
+ DUMP_WED(WED_RX_MSDU_PG_CNT(5)),
|
|
+ DUMP_WED_MASK(WED_RX_PN_CHK_CNT,
|
|
+ WED_PN_CHK_FAIL_CNT),
|
|
+ };
|
|
+ struct mtk_wed_hw *hw = s->private;
|
|
+ struct mtk_wed_device *dev = hw->wed_dev;
|
|
+
|
|
+ if (dev)
|
|
+ dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+DEFINE_SHOW_ATTRIBUTE(wed_rro);
|
|
+
|
|
+static int
|
|
mtk_wed_reg_set(void *data, u64 val)
|
|
{
|
|
struct mtk_wed_hw *hw = data;
|
|
@@ -266,7 +624,16 @@ void mtk_wed_hw_add_debugfs(struct mtk_w
|
|
debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
|
|
debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval);
|
|
debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops);
|
|
- if (!mtk_wed_is_v1(hw))
|
|
+ if (!mtk_wed_is_v1(hw)) {
|
|
debugfs_create_file_unsafe("rxinfo", 0400, dir, hw,
|
|
&wed_rxinfo_fops);
|
|
+ if (mtk_wed_is_v3_or_greater(hw)) {
|
|
+ debugfs_create_file_unsafe("amsdu", 0400, dir, hw,
|
|
+ &wed_amsdu_fops);
|
|
+ debugfs_create_file_unsafe("rtqm", 0400, dir, hw,
|
|
+ &wed_rtqm_fops);
|
|
+ debugfs_create_file_unsafe("rro", 0400, dir, hw,
|
|
+ &wed_rro_fops);
|
|
+ }
|
|
+ }
|
|
}
|