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9a417fbd0d
Refreshed all patches. Compile-tested on: ipq40xx, ramips Runtime-tested on: ipq40xx Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
169 lines
5.5 KiB
Diff
169 lines
5.5 KiB
Diff
From 9257240bcaf8f9ee6878357e00e7ab511ad6d325 Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 16 Oct 2017 09:46:35 +0800
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Subject: [PATCH 156/224] mmc: mediatek: add stop_clk fix and enhance_rx
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support
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mt2712 supports stop_clk fix and enhance_rx, which can improve
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host stability.
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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Tested-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/mtk-sd.c | 47 +++++++++++++++++++++++++++++++++++++++++++----
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1 file changed, 43 insertions(+), 4 deletions(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -67,6 +67,7 @@
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#define SDC_RESP2 0x48
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#define SDC_RESP3 0x4c
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#define SDC_BLK_NUM 0x50
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+#define SDC_ADV_CFG0 0x64
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#define EMMC_IOCON 0x7c
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#define SDC_ACMD_RESP 0x80
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#define MSDC_DMA_SA 0x90
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@@ -80,6 +81,7 @@
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#define PAD_DS_TUNE 0x188
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#define PAD_CMD_TUNE 0x18c
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#define EMMC50_CFG0 0x208
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+#define SDC_FIFO_CFG 0x228
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/*--------------------------------------------------------------------------*/
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/* Register Mask */
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@@ -188,6 +190,9 @@
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#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
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#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
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+/* SDC_ADV_CFG0 mask */
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+#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
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+
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/* MSDC_DMA_CTRL mask */
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#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
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#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
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@@ -219,6 +224,8 @@
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#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
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+#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
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+
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#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
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#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
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#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
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@@ -244,6 +251,9 @@
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#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
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#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
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+#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
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+#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
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+
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#define REQ_CMD_EIO (0x1 << 0)
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#define REQ_CMD_TMO (0x1 << 1)
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#define REQ_DAT_ERR (0x1 << 2)
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@@ -310,6 +320,7 @@ struct msdc_save_para {
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u32 pad_ds_tune;
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u32 pad_cmd_tune;
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u32 emmc50_cfg0;
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+ u32 sdc_fifo_cfg;
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};
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struct mtk_mmc_compatible {
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@@ -319,6 +330,8 @@ struct mtk_mmc_compatible {
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bool async_fifo;
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bool data_tune;
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bool busy_check;
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+ bool stop_clk_fix;
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+ bool enhance_rx;
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};
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struct msdc_tune_para {
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@@ -384,6 +397,8 @@ static const struct mtk_mmc_compatible m
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.async_fifo = false,
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.data_tune = false,
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.busy_check = false,
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+ .stop_clk_fix = false,
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+ .enhance_rx = false,
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};
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static const struct mtk_mmc_compatible mt8173_compat = {
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@@ -393,6 +408,8 @@ static const struct mtk_mmc_compatible m
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.async_fifo = false,
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.data_tune = false,
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.busy_check = false,
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+ .stop_clk_fix = false,
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+ .enhance_rx = false,
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};
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static const struct mtk_mmc_compatible mt2701_compat = {
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@@ -402,6 +419,8 @@ static const struct mtk_mmc_compatible m
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.async_fifo = true,
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.data_tune = true,
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.busy_check = false,
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+ .stop_clk_fix = false,
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+ .enhance_rx = false,
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};
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static const struct mtk_mmc_compatible mt2712_compat = {
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@@ -411,6 +430,8 @@ static const struct mtk_mmc_compatible m
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.async_fifo = true,
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.data_tune = true,
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.busy_check = true,
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+ .stop_clk_fix = true,
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+ .enhance_rx = true,
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};
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static const struct of_device_id msdc_of_ids[] = {
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@@ -1282,15 +1303,31 @@ static void msdc_init_hw(struct msdc_hos
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sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
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+
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+ if (host->dev_comp->stop_clk_fix) {
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+ sdr_set_field(host->base + MSDC_PATCH_BIT1,
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+ MSDC_PATCH_BIT1_STOP_DLY, 3);
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+ sdr_clr_bits(host->base + SDC_FIFO_CFG,
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+ SDC_FIFO_CFG_WRVALIDSEL);
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+ sdr_clr_bits(host->base + SDC_FIFO_CFG,
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+ SDC_FIFO_CFG_RDVALIDSEL);
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+ }
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+
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if (host->dev_comp->busy_check)
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sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
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+
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if (host->dev_comp->async_fifo) {
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sdr_set_field(host->base + MSDC_PATCH_BIT2,
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MSDC_PB2_RESPWAIT, 3);
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- sdr_set_field(host->base + MSDC_PATCH_BIT2,
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- MSDC_PB2_RESPSTSENSEL, 2);
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- sdr_set_field(host->base + MSDC_PATCH_BIT2,
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- MSDC_PB2_CRCSTSENSEL, 2);
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+ if (host->dev_comp->enhance_rx) {
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+ sdr_set_bits(host->base + SDC_ADV_CFG0,
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+ SDC_RX_ENHANCE_EN);
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+ } else {
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+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
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+ MSDC_PB2_RESPSTSENSEL, 2);
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+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
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+ MSDC_PB2_CRCSTSENSEL, 2);
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+ }
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/* use async fifo, then no need tune internal delay */
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sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
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MSDC_PATCH_BIT2_CFGRESP);
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@@ -1936,6 +1973,7 @@ static void msdc_save_reg(struct msdc_ho
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host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
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host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
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host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
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+ host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
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}
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static void msdc_restore_reg(struct msdc_host *host)
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@@ -1952,6 +1990,7 @@ static void msdc_restore_reg(struct msdc
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writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
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writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
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writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
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+ writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
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}
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static int msdc_runtime_suspend(struct device *dev)
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