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10c5d3dd5f
SoC: Mediatek MT7621A
CPU: 4x 880Mhz
Cache: 32 KB I-Cache and 32 KB D-Cach
256 KB L2 Cache (shared by Dual-Core)
RAM: DDR3 512MB 16bits BUS
FLASH: 16MB
Switch: Mediatek Gigabit Switch (2 x LAN, 1 x WAN)
POE: (1x PD, 2x PSE)
USB: 1x 3.0
PCI: 3x Mini PCIe (3 USB2.0 + 2 x UIM interface)
GPS: Quectel L70B
SIM: 2 Slots
BTN: Reset
LED: - Power
- Ethernet
- Wifi
- USB
UART: UART is present as Pads with throughholes on the PCB.
They are located on left side.
3.3V - RX - GND - TX / 57600-8N1
3.3V is the square pad
Installation
------------
The stock image is a modified openwrt and can be overflashed via sysupgrade -F
Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
[merge conflict in mt7621.mk]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
121 lines
1.8 KiB
Plaintext
121 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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wlan1 {
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label = "ap7621-001:orange:wlan1";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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};
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wlan0 {
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label = "ap7621-001:orange:wlan0";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&sdhci {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x2000>;
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};
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partition@32000 {
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label = "2860";
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reg = <0x32000 0x4000>;
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};
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partition@36000 {
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label = "rtdev";
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reg = <0x36000 0x2000>;
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};
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partition@38000 {
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label = "Reserve";
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reg = <0x38000 0x8000>;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "firmware";
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reg = <0x50000 0xfa0000>;
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compatible = "denx,uimage";
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};
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partition@ff0000 {
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label = "nvram";
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reg = <0xff0000 0x10000>;
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read-only;
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};
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};
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};
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};
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&pcie {
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status = "okay";
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};
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ðernet {
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mtd-mac-address = <&factory 0xe000>;
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mediatek,portmap = "llllw";
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "wdt", "jtag";
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ralink,function = "gpio";
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};
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};
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};
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