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https://github.com/openwrt/openwrt.git
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1a8218d6e4
This contains the following new bigger changes: * new partition parser which still could lake some features or have bugs * new nand flash driver * using physmap-flash flash driver for parallel flash * some changes to the serial flash driver With these changes OpenWrt starts using more of the mainline flash drivers. SVN-Revision: 35632
178 lines
4.4 KiB
Diff
178 lines
4.4 KiB
Diff
--- a/arch/mips/bcm47xx/nvram.c
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+++ b/arch/mips/bcm47xx/nvram.c
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@@ -198,3 +198,30 @@ int bcm47xx_nvram_getenv(char *name, cha
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return -ENOENT;
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}
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EXPORT_SYMBOL(bcm47xx_nvram_getenv);
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+
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+char *nvram_get(const char *name)
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+{
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+ char *var, *value, *end, *eq;
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+
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+ if (!name)
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+ return NULL;
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+
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+ if (!nvram_buf[0])
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+ nvram_init();
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+
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+ /* Look for name=value and return value */
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+ var = &nvram_buf[sizeof(struct nvram_header)];
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+ end = nvram_buf + sizeof(nvram_buf) - 2;
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+ end[0] = end[1] = '\0';
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+ for (; *var; var = value + strlen(value) + 1) {
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+ eq = strchr(var, '=');
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+ if (!eq)
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+ break;
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+ value = eq + 1;
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+ if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
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+ return value;
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+ }
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+
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+ return NULL;
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+}
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+EXPORT_SYMBOL(nvram_get);
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--- a/arch/mips/bcm47xx/Makefile
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+++ b/arch/mips/bcm47xx/Makefile
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@@ -5,4 +5,5 @@
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obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
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obj-y += board.o
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+obj-y += gpio.o
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obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
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--- /dev/null
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+++ b/arch/mips/bcm47xx/gpio.c
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@@ -0,0 +1,119 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
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+ * Copyright (C) 2012 Hauke Mehrtens <hauke@hauke-m.de>
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+ *
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+ * Parts of this file are based on Atheros AR71XX/AR724X/AR913X GPIO
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+ */
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+
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+#include <linux/export.h>
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+#include <linux/gpio.h>
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+#include <linux/ssb/ssb_embedded.h>
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+#include <linux/bcma/bcma.h>
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+
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+#include <bcm47xx.h>
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+
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+/* low level BCM47xx gpio api */
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+u32 bcm47xx_gpio_in(u32 mask)
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+{
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+ switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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+ case BCM47XX_BUS_TYPE_SSB:
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+ return ssb_gpio_in(&bcm47xx_bus.ssb, mask);
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc, mask);
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+#endif
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+ }
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+ return -EINVAL;
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+}
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+EXPORT_SYMBOL(bcm47xx_gpio_in);
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+
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+u32 bcm47xx_gpio_out(u32 mask, u32 value)
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+{
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+ switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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+ case BCM47XX_BUS_TYPE_SSB:
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+ return ssb_gpio_out(&bcm47xx_bus.ssb, mask, value);
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, mask,
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+ value);
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+#endif
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+ }
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+ return -EINVAL;
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+}
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+EXPORT_SYMBOL(bcm47xx_gpio_out);
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+
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+u32 bcm47xx_gpio_outen(u32 mask, u32 value)
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+{
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+ switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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+ case BCM47XX_BUS_TYPE_SSB:
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+ return ssb_gpio_outen(&bcm47xx_bus.ssb, mask, value);
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc,
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+ mask, value);
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+#endif
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+ }
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+ return -EINVAL;
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+}
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+EXPORT_SYMBOL(bcm47xx_gpio_outen);
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+
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+u32 bcm47xx_gpio_control(u32 mask, u32 value)
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+{
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+ switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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+ case BCM47XX_BUS_TYPE_SSB:
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+ return ssb_gpio_control(&bcm47xx_bus.ssb, mask, value);
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return bcma_chipco_gpio_control(&bcm47xx_bus.bcma.bus.drv_cc,
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+ mask, value);
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+#endif
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+ }
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+ return -EINVAL;
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+}
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+EXPORT_SYMBOL(bcm47xx_gpio_control);
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+
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+u32 bcm47xx_gpio_intmask(u32 mask, u32 value)
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+{
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+ switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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+ case BCM47XX_BUS_TYPE_SSB:
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+ return ssb_gpio_intmask(&bcm47xx_bus.ssb, mask, value);
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc,
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+ mask, value);
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+#endif
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+ }
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+ return -EINVAL;
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+}
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+EXPORT_SYMBOL(bcm47xx_gpio_intmask);
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+
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+u32 bcm47xx_gpio_polarity(u32 mask, u32 value)
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+{
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+ switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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+ case BCM47XX_BUS_TYPE_SSB:
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+ return ssb_gpio_polarity(&bcm47xx_bus.ssb, mask, value);
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc,
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+ mask, value);
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+#endif
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+ }
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+ return -EINVAL;
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+}
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+EXPORT_SYMBOL(bcm47xx_gpio_polarity);
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--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
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+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
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@@ -14,4 +14,11 @@ static inline int irq_to_gpio(unsigned i
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return -EINVAL;
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}
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+u32 bcm47xx_gpio_in(u32 mask);
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+u32 bcm47xx_gpio_out(u32 mask, u32 value);
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+u32 bcm47xx_gpio_outen(u32 mask, u32 value);
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+u32 bcm47xx_gpio_control(u32 mask, u32 value);
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+u32 bcm47xx_gpio_intmask(u32 mask, u32 value);
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+u32 bcm47xx_gpio_polarity(u32 mask, u32 value);
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+
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#endif
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