openwrt/target/linux/ramips/dts/mt7628an_tplink_archer-c50-v3.dts
Mieczyslaw Nalewaj b0d418035e ramips: tplink_8m: cleaning up nvmem-cells definitions
Move nvmem-cells definitions to dts files for compatibility with other files
in which mt7628an_tplink_8m.dtsi is loaded, to prevent overwriting

Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
2024-06-16 21:24:11 +02:00

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#include <dt-bindings/leds/common.h>
#include "mt7628an_tplink_8m.dtsi"
/ {
compatible = "tplink,archer-c50-v3", "mediatek,mt7628an-soc";
model = "TP-Link Archer C50 v3";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
rfkill {
label = "rfkill";
gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
leds {
compatible = "gpio-leds";
lan {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
};
led_power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
wan {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
};
wan_orange {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_ORANGE>;
gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
};
wlan {
label = "green:wlan2g";
gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
};
wlan5 {
label = "green:wlan5g";
gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
};
wps {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
};
};
};
&ehci {
status = "disabled";
};
&ohci {
status = "disabled";
};
&state_default {
gpio {
groups = "i2c", "gpio", "p0led_an", "p1led_an", "p2led_an",
"p3led_an", "p4led_an", "wdt", "wled_an";
function = "gpio";
};
};
&wmac {
status = "okay";
nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_f100 0>;
nvmem-cell-names = "eeprom", "mac-address";
};
&ethernet {
nvmem-cells = <&macaddr_factory_f100 0>;
nvmem-cell-names = "mac-address";
};
&esw {
mediatek,portmap = <0x3e>;
};
&pcie {
status = "okay";
};
&pcie0 {
mt76@0,0 {
reg = <0x0000 0 0 0 0>;
ieee80211-freq-limit = <5000000 6000000>;
nvmem-cells = <&eeprom_factory_28000>, <&macaddr_factory_f100 (-1)>;
nvmem-cell-names = "eeprom", "mac-address";
};
};