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0a827ebd2f
This patch is to upgrade kernel to 4.14 for layerscape. patches-4.14 for layerscape included two categories. - NXP Layerscape SDK kernel-4.14 patches All patches on tag LSDK-18.09-V4.14 were ported to OpenWrt kernel. Since there were hundreds patches, we had to make an all-in-one patch for each IP/feature. See below links for LSDK kernel. https://lsdk.github.io/components.html https://source.codeaurora.org/external/qoriq/qoriq-components/linux - Non-LSDK kernel patches Other patches which were not in LSDK were just put in patches-4.14. Kept below patches from patches-4.9. 303-dts-layerscape-add-traverse-ls1043.patch 821-add-esdhc-vsel-to-ls1043.patch 822-rgmii-fixed-link.patch Renamed and rebase them as below in patches-4.14, 303-add-DTS-for-Traverse-LS1043-Boards.patch 712-sdk-dpaa-rgmii-fixed-link.patch 824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com>
69 lines
2.8 KiB
Diff
69 lines
2.8 KiB
Diff
From 918f966af1f0e42ff8ac298e1d7d02e67afcfab4 Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Tue, 30 Oct 2018 18:27:42 +0800
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Subject: [PATCH 18/40] sata: support layerscape
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This is an integrated patch of sata for layerscape
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Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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---
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drivers/ata/ahci_qoriq.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/drivers/ata/ahci_qoriq.c
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+++ b/drivers/ata/ahci_qoriq.c
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@@ -35,6 +35,8 @@
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/* port register default value */
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#define AHCI_PORT_PHY_1_CFG 0xa003fffe
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+#define AHCI_PORT_PHY2_CFG 0x28184d1f
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+#define AHCI_PORT_PHY3_CFG 0x0e081509
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#define AHCI_PORT_TRANS_CFG 0x08000029
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#define AHCI_PORT_AXICC_CFG 0x3fffffff
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@@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ah
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writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
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qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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@@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ah
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case AHCI_LS2080A:
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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@@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ah
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writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
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qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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@@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ah
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writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
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qpriv->ecc_addr);
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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@@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ah
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case AHCI_LS2088A:
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
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+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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if (qpriv->is_dmacoherent)
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writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
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