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b40e6bc55f
In ath79, for several SoCs the console bootargs are defined to the
very same value in every device's DTS. Consolidate these definitions
in the SoC dtsi files and drop further redundant definitions elsewhere.
The only device without any bootargs set has been OpenMesh OM5P-AC V2.
This will now inherit the setting from qca955x.dtsi
While this is a cosmetic change, backporting it to 19.07 will be a
major help for anyone doing backports of device support. Without it,
every backporter would have to remember to manually add the chosen node
to the device's DTS.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 635f111148)
173 lines
2.8 KiB
Plaintext
173 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "qca956x.dtsi"
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/ {
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model = "NEC Aterm WG1200CR";
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compatible = "nec,wg1200cr", "qca,qca9563";
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aliases {
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led-boot = &power_green;
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led-failsafe = &power_red;
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led-running = &power_green;
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led-upgrade = &power_green;
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};
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leds {
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compatible = "gpio-leds";
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/* other LEDs are connected to ath10k (QCA9888) gpiochip */
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power_green: power_green {
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label = "wg1200cr:green:power";
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gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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power_red: power_red {
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label = "wg1200cr:red:power";
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gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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debounce-interval = <60>;
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};
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wps {
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label = "wps";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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debounce-interval = <60>;
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};
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bridge {
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label = "br";
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gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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linux,input-type = <EV_SW>;
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debounce-interval = <60>;
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};
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converter {
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label = "cnv";
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gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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linux,input-type = <EV_SW>;
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debounce-interval = <60>;
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};
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};
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};
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&spi {
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status = "okay";
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num-cs = <1>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x000000 0x040000>;
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read-only;
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};
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partition@40000 {
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label = "devdata";
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reg = <0x040000 0x010000>;
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read-only;
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};
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partition@50000 {
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label = "devconf";
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reg = <0x050000 0x010000>;
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read-only;
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};
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partition@60000 {
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label = "misc";
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reg = <0x060000 0x010000>;
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read-only;
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};
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partition@70000 {
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label = "wifimngdata";
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reg = <0x070000 0x010000>;
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read-only;
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};
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partition@80000 {
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compatible = "seama";
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label = "firmware";
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reg = <0x080000 0x770000>;
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};
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partition@7f0000 {
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label = "art";
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reg = <0x7f0000 0x010000>;
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read-only;
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};
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};
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};
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};
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&mdio0 {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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qca,ar8327-initvals = <
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0x04 0x00000080 /* PORT0 PAD MODE CTRL */
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0x50 0xcc35cc35 /* LED_CTRL0 */
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0x54 0xca35ca35 /* LED_CTRL1 */
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0x58 0xc935c935 /* LED_CTRL2 */
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0x5c 0x03ffff00 /* LED_CTRL3 */
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0x7c 0x0000007e /* PORT0_STATUS */
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>;
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};
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};
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ð0 {
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status = "okay";
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pll-data = <0x03000101 0x00000101 0x00001919>;
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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};
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&pcie {
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status = "okay";
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wifi@0,0 {
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compatible = "pci168c,0056";
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reg = <0x0000 0 0 0 0>;
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};
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};
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&uart {
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status = "okay";
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};
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&wmac {
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status = "okay";
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qca,no-eeprom;
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};
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