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f02f6aaa8d
Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
37 lines
1.3 KiB
Diff
37 lines
1.3 KiB
Diff
From f5aaf6669bd4f1f0218dd7fd5dc90941267ad860 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Tue, 30 May 2023 23:26:30 +0200
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Subject: [PATCH] mmc: core: disable TRIM on Micron MTFC4GACAJCN-1M
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It seems that Micron MTFC4GACAJCN-1M despite advertising TRIM support does
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not work when the core is trying to use REQ_OP_WRITE_ZEROES.
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We are seeing the following errors in OpenWrt under 6.1 on Qnap Qhora 301W
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that we did not previously have and tracked it down to REQ_OP_WRITE_ZEROES:
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[ 18.085950] I/O error, dev loop0, sector 596 op 0x9:(WRITE_ZEROES) flags 0x800 phys_seg 0 prio class 2
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Disabling TRIM makes the error go away, so lets add a quirk for this eMMC
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to disable TRIM.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/mmc/core/quirks.h | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/drivers/mmc/core/quirks.h
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+++ b/drivers/mmc/core/quirks.h
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@@ -101,6 +101,13 @@ static const struct mmc_fixup __maybe_un
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MMC_QUIRK_TRIM_BROKEN),
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/*
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+ * Micron MTFC4GACAJCN-1M advertises TRIM but it does not seems to
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+ * support being used to offload WRITE_ZEROES.
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+ */
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+ MMC_FIXUP("Q2J54A", CID_MANFID_MICRON, 0x014e, add_quirk_mmc,
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+ MMC_QUIRK_TRIM_BROKEN),
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+
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+ /*
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* Some SD cards reports discard support while they don't
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*/
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MMC_FIXUP(CID_NAME_ANY, CID_MANFID_SANDISK_SD, 0x5344, add_quirk_sd,
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