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Some BCM63xx SoCs support multiple CPU frequencies depending on HW configuration. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
240 lines
6.3 KiB
Diff
240 lines
6.3 KiB
Diff
From 38d5e4b3bcc25db14a2d5f428acf56dff862c97e Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Fri, 5 Mar 2021 15:14:32 +0100
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Subject: [PATCH] bmips: automatically detect CPU frequency
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Some BCM63xx SoCs support multiple CPU frequencies depending on HW config.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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---
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arch/mips/bmips/setup.c | 197 +++++++++++++++++++++-
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arch/mips/configs/bmips_bcm63xx_defconfig | 91 ++++++++++
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2 files changed, 281 insertions(+), 7 deletions(-)
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create mode 100644 arch/mips/configs/bmips_bcm63xx_defconfig
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--- a/arch/mips/bmips/setup.c
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+++ b/arch/mips/bmips/setup.c
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@@ -31,11 +31,51 @@
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#define RELO_NORMAL_VEC BIT(18)
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+#define REG_BCM6318_SOB ((void __iomem *)CKSEG1ADDR(0x10000900))
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+#define BCM6318_FREQ_SHIFT 23
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+#define BCM6318_FREQ_MASK (0x3 << BCM6318_FREQ_SHIFT)
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+
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#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
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#define BCM6328_TP1_DISABLED BIT(9)
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+#define REG_BCM6328_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001a40))
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+#define BCM6328_FCVO_SHIFT 7
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+#define BCM6328_FCVO_MASK (0x1f << BCM6328_FCVO_SHIFT)
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+
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+#define REG_BCM6358_DDR_PLLC ((void __iomem *)CKSEG1ADDR(0x100012b8))
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+#define BCM6358_PLLC_M1_SHIFT 0
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+#define BCM6358_PLLC_M1_MASK (0xff << BCM6358_PLLC_M1_SHIFT)
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+#define BCM6358_PLLC_N1_SHIFT 23
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+#define BCM6358_PLLC_N1_MASK (0x3f << BCM6358_PLLC_N1_SHIFT)
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+#define BCM6358_PLLC_N2_SHIFT 29
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+#define BCM6358_PLLC_N2_MASK (0x7 << BCM6358_PLLC_N2_SHIFT)
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+
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+#define REG_BCM6362_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001814))
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+#define BCM6362_FCVO_SHIFT 1
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+#define BCM6362_FCVO_MASK (0x1f << BCM6362_FCVO_SHIFT)
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+
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+#define REG_BCM6368_DDR_PLLC ((void __iomem *)CKSEG1ADDR(0x100012a0))
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+#define BCM6368_PLLC_P1_SHIFT 0
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+#define BCM6368_PLLC_P1_MASK (0xf << BCM6368_PLLC_P1_SHIFT)
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+#define BCM6368_PLLC_P2_SHIFT 4
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+#define BCM6368_PLLC_P2_MASK (0xf << BCM6368_PLLC_P2_SHIFT)
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+#define BCM6368_PLLC_NDIV_SHIFT 16
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+#define BCM6368_PLLC_NDIV_MASK (0x1ff << BCM6368_PLLC_NDIV_SHIFT)
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+#define REG_BCM6368_DDR_PLLD ((void __iomem *)CKSEG1ADDR(0x100012a4))
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+#define BCM6368_PLLD_MDIV_SHIFT 0
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+#define BCM6368_PLLD_MDIV_MASK (0xff << BCM6368_PLLD_MDIV_SHIFT)
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+
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+#define REG_BCM63268_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001814))
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+#define BCM63268_FCVO_SHIFT 21
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+#define BCM63268_FCVO_MASK (0xf << BCM63268_FCVO_SHIFT)
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+
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static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
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+struct bmips_cpufreq {
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+ const char *compatible;
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+ u32 (*cpu_freq)(void);
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+};
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+
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struct bmips_quirk {
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const char *compatible;
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void (*quirk_fn)(void);
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@@ -138,17 +178,160 @@ const char *get_system_type(void)
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return "Generic BMIPS kernel";
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}
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+static u32 bcm6318_cpufreq(void)
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+{
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+ u32 val = __raw_readl(REG_BCM6318_SOB);
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+
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+ switch ((val & BCM6318_FREQ_MASK) >> BCM6318_FREQ_SHIFT) {
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+ case 0:
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+ return 166000000;
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+ case 2:
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+ return 250000000;
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+ case 3:
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+ return 333000000;
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+ case 1:
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+ return 400000000;
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+ default:
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+ return 0;
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+ }
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+}
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+
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+static u32 bcm6328_cpufreq(void)
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+{
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+ u32 val = __raw_readl(REG_BCM6328_MISC_SB);
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+
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+ switch ((val & BCM6328_FCVO_MASK) >> BCM6328_FCVO_SHIFT) {
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+ case 0x12:
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+ case 0x14:
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+ case 0x19:
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+ return 160000000;
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+ case 0x1c:
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+ return 192000000;
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+ case 0x13:
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+ case 0x15:
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+ return 200000000;
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+ case 0x1a:
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+ return 384000000;
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+ case 0x16:
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+ return 400000000;
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+ default:
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+ return 320000000;
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+ }
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+}
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+
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+static u32 bcm6358_cpufreq(void)
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+{
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+ u32 val, n1, n2, m1;
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+
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+ val = __raw_readl(REG_BCM6358_DDR_PLLC);
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+ n1 = (val & BCM6358_PLLC_M1_MASK) >> BCM6358_PLLC_N1_SHIFT;
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+ n2 = (val & BCM6358_PLLC_N2_MASK) >> BCM6358_PLLC_N2_SHIFT;
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+ m1 = (val & BCM6358_PLLC_M1_MASK) >> BCM6358_PLLC_M1_SHIFT;
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+
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+ return (16 * 1000000 * n1 * n2) / m1;
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+}
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+
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+static u32 bcm6362_cpufreq(void)
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+{
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+ u32 val = __raw_readl(REG_BCM6362_MISC_SB);
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+
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+ switch ((val & BCM6362_FCVO_MASK) >> BCM6362_FCVO_SHIFT) {
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+ case 0x04:
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+ case 0x0c:
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+ case 0x14:
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+ case 0x1c:
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+ return 160000000;
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+ case 0x15:
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+ case 0x1d:
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+ return 200000000;
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+ case 0x03:
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+ case 0x0b:
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+ case 0x13:
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+ case 0x1b:
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+ return 240000000;
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+ case 0x07:
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+ case 0x17:
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+ return 384000000;
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+ case 0x05:
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+ case 0x0e:
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+ case 0x16:
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+ case 0x1e:
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+ case 0x1f:
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+ return 400000000;
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+ case 0x06:
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+ return 440000000;
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+ default:
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+ return 320000000;
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+ }
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+}
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+
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+static u32 bcm6368_cpufreq(void)
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+{
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+ unsigned int val, p1, p2, ndiv, m1;
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+
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+ val = __raw_readl(REG_BCM6368_DDR_PLLC);
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+ p1 = (val & BCM6368_PLLC_P1_MASK) >> BCM6368_PLLC_P1_SHIFT;
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+ p2 = (val & BCM6368_PLLC_P2_MASK) >> BCM6368_PLLC_P2_SHIFT;
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+ ndiv = (val & BCM6368_PLLC_NDIV_MASK) >>
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+ BCM6368_PLLC_NDIV_SHIFT;
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+
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+ val = __raw_readl(REG_BCM6368_DDR_PLLD);
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+ m1 = (val & BCM6368_PLLD_MDIV_MASK) >> BCM6368_PLLD_MDIV_SHIFT;
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+
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+ return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
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+}
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+
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+static u32 bcm63268_cpufreq(void)
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+{
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+ u32 val = __raw_readl(REG_BCM63268_MISC_SB);
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+
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+ switch ((val & BCM63268_FCVO_MASK) >> BCM63268_FCVO_SHIFT) {
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+ case 0x3:
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+ case 0xe:
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+ return 320000000;
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+ case 0xa:
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+ return 333000000;
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+ case 0x2:
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+ case 0xb:
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+ case 0xf:
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+ return 400000000;
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+ default:
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+ return 0;
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+ }
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+}
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+
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+static const struct bmips_cpufreq bmips_cpufreq_list[] = {
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+ { "brcm,bcm6318", &bcm6318_cpufreq },
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+ { "brcm,bcm6328", &bcm6328_cpufreq },
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+ { "brcm,bcm6358", &bcm6358_cpufreq },
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+ { "brcm,bcm6362", &bcm6362_cpufreq },
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+ { "brcm,bcm6368", &bcm6368_cpufreq },
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+ { "brcm,bcm63268", &bcm63268_cpufreq },
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+ { /* sentinel */ }
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+};
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+
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void __init plat_time_init(void)
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{
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+ const struct bmips_cpufreq *cf;
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struct device_node *np;
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- u32 freq;
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+ u32 freq = 0;
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- np = of_find_node_by_name(NULL, "cpus");
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- if (!np)
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- panic("missing 'cpus' DT node");
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- if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
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- panic("missing 'mips-hpt-frequency' property");
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- of_node_put(np);
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+ for (cf = bmips_cpufreq_list; cf->cpu_freq; cf++) {
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+ if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
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+ cf->compatible)) {
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+ freq = cf->cpu_freq() / 2;
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+ printk("%s detected @ %u MHz\n", cf->compatible, freq / 500000);
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+ }
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+ }
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+
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+ if (!freq) {
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+ np = of_find_node_by_name(NULL, "cpus");
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+ if (!np)
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+ panic("missing 'cpus' DT node");
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+ if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
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+ panic("missing 'mips-hpt-frequency' property");
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+ of_node_put(np);
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+ }
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mips_hpt_frequency = freq;
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}
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