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2e715fb4fc
Add support for BCM2712 (Raspberry Pi 5).
3bb5880ab3
Patches were generated from the diff between linux kernel branch linux-6.1.y
and rpi-6.1.y from raspberry pi kernel source:
- git format-patch linux-6.1.y...rpi-6.1.y
Build system: x86_64
Build-tested: bcm2708, bcm2709, bcm2710, bcm2711
Run-tested: bcm2710/RPi3B, bcm2711/RPi4B
Signed-off-by: Marty Jones <mj8263788@gmail.com>
[Remove applied and reverted patches, squash patches and config commits]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
101 lines
2.6 KiB
Diff
101 lines
2.6 KiB
Diff
From bcf02f6ac0d429a425e8409f140bd875a1feed2e Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Thu, 27 Apr 2023 13:46:53 +0200
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Subject: [PATCH] drm/vc4: hvs: Test if the EOF interrupts are enabled
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We currently enable the EOF interrupts through the CRTC destroy_state
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implementation.
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However, nothing guarantees that we can't call destroy_state multiple
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times in a row, and therefore before the EOF interrupt even happens.
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This means we would enable the interrupt multiple times but disable it
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only once. It wasn't an issue so far since the interrupts were only
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enabled by setting a bit in a register, but with BCM2712 we will use an
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external interrupt controller, with a refcounted interrupt.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_drv.h | 8 ++++++--
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drivers/gpu/drm/vc4/vc4_hvs.c | 14 ++++++++++++--
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2 files changed, 18 insertions(+), 4 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -333,6 +333,8 @@ struct vc4_v3d {
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struct debugfs_regset32 regset;
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};
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+#define HVS_NUM_CHANNELS 3
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+
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struct vc4_hvs {
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struct vc4_dev *vc4;
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struct platform_device *pdev;
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@@ -341,6 +343,10 @@ struct vc4_hvs {
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struct clk *core_clk;
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+ struct {
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+ unsigned int enabled: 1;
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+ } eof_irq[HVS_NUM_CHANNELS];
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+
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unsigned long max_core_rate;
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/* Memory manager for CRTCs to allocate space in the display
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@@ -373,8 +379,6 @@ struct vc4_hvs {
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bool vc5_hdmi_enable_4096by2160;
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};
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-#define HVS_NUM_CHANNELS 3
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-
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struct vc4_hvs_state {
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struct drm_private_state base;
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unsigned long core_clock_rate;
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -412,11 +412,14 @@ static void vc5_hvs_update_gamma_lut(str
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vc5_hvs_lut_load(hvs, vc4_crtc);
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}
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-static void vc4_hvs_irq_enable_eof(const struct vc4_hvs *hvs,
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+static void vc4_hvs_irq_enable_eof(struct vc4_hvs *hvs,
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unsigned int channel)
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{
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struct vc4_dev *vc4 = hvs->vc4;
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+ if (hvs->eof_irq[channel].enabled)
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+ return;
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+
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switch (vc4->gen) {
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case VC4_GEN_4:
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HVS_WRITE(SCALER_DISPCTRL,
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@@ -433,13 +436,18 @@ static void vc4_hvs_irq_enable_eof(const
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default:
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break;
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}
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+
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+ hvs->eof_irq[channel].enabled = true;
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}
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-static void vc4_hvs_irq_clear_eof(const struct vc4_hvs *hvs,
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+static void vc4_hvs_irq_clear_eof(struct vc4_hvs *hvs,
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unsigned int channel)
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{
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struct vc4_dev *vc4 = hvs->vc4;
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+ if (!hvs->eof_irq[channel].enabled)
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+ return;
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+
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switch (vc4->gen) {
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case VC4_GEN_4:
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HVS_WRITE(SCALER_DISPCTRL,
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@@ -456,6 +464,8 @@ static void vc4_hvs_irq_clear_eof(const
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default:
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break;
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}
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+
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+ hvs->eof_irq[channel].enabled = false;
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}
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static struct vc4_hvs_dlist_allocation *
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