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0976b6c426
Set the PHY base address to 12 for mt7530 and 8 for others, which is based on the default setting for some devices from printing the register with the following command after it is written to by uboot during the boot cycle. `md 0x10117014 1` PHY_BASE option only uses 5 bits of the register, bits 16 to 20, so use 8-bit integer type. Set the option using the DTS property mediatek,ephy-base and create the gsw node if missing. Also, added a kernel message to display the EPHY base address. Note: If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf) then there is adverse effects with Atheros switches. Signed-off-by: Michael Pratt <mcpratt@pm.me>
180 lines
2.7 KiB
Plaintext
180 lines
2.7 KiB
Plaintext
#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "sercomm,na930", "ralink,mt7620a-soc";
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model = "Sercomm NA930";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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chosen {
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bootargs = "console=ttyS1,57600";
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};
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nand {
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compatible = "mtk,mt7620-nand";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x20000>;
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read-only;
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};
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partition@200000 {
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label = "factory";
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reg = <0x200000 0x40000>;
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read-only;
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};
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partition@240000 {
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label = "Config";
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reg = <0x240000 0x400000>;
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read-only;
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};
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partition@640000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x640000 0x1400000>;
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};
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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zwave {
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label = "zwave";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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wps {
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label = "wps";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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zwave {
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label = "blue:zwave";
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gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
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};
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status {
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label = "blue:status";
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gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
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trigger-sources = <&ohci_port1>, <&ehci_port1>;
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linux,default-trigger = "usbport";
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};
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service {
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label = "blue:service";
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gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
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};
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led_power: power {
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label = "blue:power";
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gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
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};
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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telit {
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gpio-export,name = "telit";
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gpio-export,output = <1>;
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gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "rgmii2", "spi", "ephy";
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function = "gpio";
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};
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uartf_gpio {
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groups = "uartf";
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function = "gpio uartf";
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};
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};
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&uart {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &mdio_pins>;
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mediatek,portmap = "llllw";
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port@4 {
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status = "okay";
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phy-handle = <&phy4>;
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phy-mode = "rgmii";
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};
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port@5 {
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status = "okay";
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phy-handle = <&phy5>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,port4-gmac;
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mediatek,ephy-base = /bits/ 8 <8>;
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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