mirror of
https://github.com/openwrt/openwrt.git
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b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
81 lines
2.2 KiB
Diff
81 lines
2.2 KiB
Diff
From da5a7765a20d34508036ba8ed1db87e546abcf4b Mon Sep 17 00:00:00 2001
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From: Yuantian Tang <andy.tang@nxp.com>
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Date: Mon, 25 May 2020 17:33:22 +0800
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Subject: [PATCH] thermal: qoriq: Update the settings for TMUv2
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For TMU v2, TMSAR registers need to be set properly to get the
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accurate temperature values.
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Also the temperature read needs to be converted to degree Celsius
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since it is in degrees Kelvin.
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Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
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---
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drivers/thermal/qoriq_thermal.c | 21 +++++++++++++++++++--
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1 file changed, 19 insertions(+), 2 deletions(-)
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--- a/drivers/thermal/qoriq_thermal.c
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+++ b/drivers/thermal/qoriq_thermal.c
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@@ -23,6 +23,7 @@
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#define TMTMIR_DEFAULT 0x0000000f
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#define TIER_DISABLE 0x0
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#define TEUMR0_V2 0x51009c00
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+#define TMSARA_V2 0xe
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#define TMU_VER1 0x1
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#define TMU_VER2 0x2
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@@ -35,6 +36,13 @@ struct qoriq_tmu_site_regs {
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u8 res0[0x8];
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};
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+struct qoriq_tmu_tmsar {
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+ u32 res0;
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+ u32 tmsar;
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+ u32 res1;
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+ u32 res2;
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+};
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+
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struct qoriq_tmu_regs_v1 {
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u32 tmr; /* Mode Register */
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u32 tsr; /* Status Register */
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@@ -95,7 +103,9 @@ struct qoriq_tmu_regs_v2 {
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u32 tscfgr; /* Sensor Configuration Register */
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u8 res6[0x78];
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struct qoriq_tmu_site_regs site[SITES_MAX];
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- u8 res7[0x9f8];
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+ u8 res10[0x100];
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+ struct qoriq_tmu_tmsar tmsar[16];
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+ u8 res7[0x7f8];
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u32 ipbrr0; /* IP Block Revision Register 0 */
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u32 ipbrr1; /* IP Block Revision Register 1 */
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u8 res8[0x300];
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@@ -158,7 +168,10 @@ static int tmu_get_temp(void *p, int *te
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u32 val;
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val = tmu_read(qdata, &qdata->regs->site[qsensor->id].tritsr);
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- *temp = (val & 0xff) * 1000;
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+ if (qdata->ver == TMU_VER1)
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+ *temp = (val & 0xff) * 1000;
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+ else
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+ *temp = (val & 0x1ff) * 1000 - 273150;
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return 0;
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}
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@@ -319,6 +332,8 @@ static int qoriq_tmu_calibration(struct
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static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
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{
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+ int i;
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+
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/* Disable interrupt, using polling instead */
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tmu_write(data, TIER_DISABLE, &data->regs->tier);
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@@ -328,6 +343,8 @@ static void qoriq_tmu_init_device(struct
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} else {
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tmu_write(data, TMTMIR_DEFAULT, &data->regs_v2->tmtmir);
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tmu_write(data, TEUMR0_V2, &data->regs_v2->teumr0);
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+ for (i = 0; i < 7; i++)
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+ tmu_write(data, TMSARA_V2, &data->regs_v2->tmsar[i].tmsar);
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}
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/* Disable monitoring */
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