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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
78 lines
2.4 KiB
Diff
78 lines
2.4 KiB
Diff
From cde57aebfd86b3b062ce0bcf71395d735d05b2f6 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Wed, 6 Apr 2022 00:38:05 +0200
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Subject: [PATCH 1018/1024] soc: sifive: ccache: Add StarFive JH71x0 support
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This adds support for the StarFive JH7100 and JH7110 SoCs which also
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feature this SiFive cache controller.
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Unfortunately the interrupt for uncorrected data is broken on the JH7100
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and fires continuously, so add a quirk to not register a handler for it.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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arch/riscv/Kconfig.socs | 1 +
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drivers/soc/sifive/Kconfig | 2 +-
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drivers/soc/sifive/sifive_ccache.c | 12 +++++++++++-
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3 files changed, 13 insertions(+), 2 deletions(-)
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--- a/arch/riscv/Kconfig.socs
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+++ b/arch/riscv/Kconfig.socs
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@@ -28,6 +28,7 @@ config SOC_STARFIVE
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bool "StarFive SoCs"
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select PINCTRL
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select RESET_CONTROLLER
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+ select SIFIVE_CCACHE
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select SIFIVE_PLIC
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select ARM_AMBA
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help
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--- a/drivers/soc/sifive/Kconfig
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+++ b/drivers/soc/sifive/Kconfig
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@@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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-if SOC_SIFIVE
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+if SOC_SIFIVE || SOC_STARFIVE
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config SIFIVE_CCACHE
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bool "Sifive Composable Cache controller"
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--- a/drivers/soc/sifive/sifive_ccache.c
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+++ b/drivers/soc/sifive/sifive_ccache.c
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@@ -106,6 +106,8 @@ static void ccache_config_read(void)
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static const struct of_device_id sifive_ccache_ids[] = {
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{ .compatible = "sifive,fu540-c000-ccache" },
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{ .compatible = "sifive,fu740-c000-ccache" },
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+ { .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) },
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+ { .compatible = "starfive,jh7110-ccache" },
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{ .compatible = "sifive,ccache0" },
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{ /* end of table */ }
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};
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@@ -210,11 +212,15 @@ static int __init sifive_ccache_init(voi
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struct device_node *np;
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struct resource res;
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int i, rc, intr_num;
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+ const struct of_device_id *match;
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+ unsigned long broken_irqs;
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- np = of_find_matching_node(NULL, sifive_ccache_ids);
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+ np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
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if (!np)
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return -ENODEV;
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+ broken_irqs = (uintptr_t)match->data;
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+
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if (of_address_to_resource(np, 0, &res)) {
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rc = -ENODEV;
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goto err_node_put;
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@@ -240,6 +246,10 @@ static int __init sifive_ccache_init(voi
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for (i = 0; i < intr_num; i++) {
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g_irq[i] = irq_of_parse_and_map(np, i);
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+
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+ if (broken_irqs & BIT(i))
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+ continue;
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+
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rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
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NULL);
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if (rc) {
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