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01d8e41c16
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.51 Removed upstreamed: generic/backport-6.6/200-regmap-maple-work-around-false-positive-warning.patch generic/backport-6.6/822-v6.11-0012-nvmem-Fix-return-type-of-devm_nvmem_device_get-in-ke.patch bcm27xx/patches-6.6/950-1018-drivers-mmc-apply-SD-quirks-earlier-during-probe.patch Manually rebased: bcm27xx/patches-6.6/950-0993-drivers-mmc-cqhci-clear-CQHCI_CTL-if-halt-fails.patch ramips/patches-6.6/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch[4] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=e42ea96d6d36a16526cb82b8aa2e5422814c3250 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=3d1baf322a3a69b38b6b2d511cfe0d611d1b5462 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=115a755bb38db5a1175be44e6a9a93a0a8233885 4. Adapted the changes from Hauke Mehrtens' modification in PR#16366 to 5.15.167 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/16370 Signed-off-by: Robert Marko <robimarko@gmail.com>
77 lines
2.3 KiB
Diff
77 lines
2.3 KiB
Diff
From 69275b667bd930cf5d5f577ba0ab1987c9d13987 Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Mon, 21 Aug 2023 23:29:15 +0800
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Subject: [PATCH 001/116] clk: starfive: jh7110-sys: Fix lower rate of CPUfreq
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by setting PLL0 rate to 1.5GHz
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CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
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But now PLL0 rate is 1GHz and the cpu frequency loads become
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333/500/500/1000MHz in fact.
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So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock
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and the divider of cpu_core before the setting.
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Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
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Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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.../clk/starfive/clk-starfive-jh7110-sys.c | 47 ++++++++++++++++++-
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1 file changed, 46 insertions(+), 1 deletion(-)
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--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
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@@ -530,7 +530,52 @@ static int __init jh7110_syscrg_probe(st
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if (ret)
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return ret;
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- return jh7110_reset_controller_register(priv, "rst-sys", 0);
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+ ret = jh7110_reset_controller_register(priv, "rst-sys", 0);
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * Set PLL0 rate to 1.5GHz
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+ * In order to not affect the cpu when the PLL0 rate is changing,
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+ * we need to switch the parent of cpu_root clock to osc clock first,
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+ * and then switch back after setting the PLL0 rate.
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+ */
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+ pllclk = clk_get(priv->dev, "pll0_out");
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+ if (!IS_ERR(pllclk)) {
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+ struct clk *osc = clk_get(&pdev->dev, "osc");
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+ struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
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+ struct clk *cpu_core = priv->reg[JH7110_SYSCLK_CPU_CORE].hw.clk;
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+
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+ if (IS_ERR(osc)) {
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+ clk_put(pllclk);
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+ return PTR_ERR(osc);
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+ }
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+
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+ /*
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+ * CPU need voltage regulation by CPUfreq if set 1.5GHz.
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+ * So in this driver, cpu_core need to be set the divider to be 2 first
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+ * and will be 750M after setting parent.
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+ */
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+ ret = clk_set_rate(cpu_core, clk_get_rate(cpu_core) / 2);
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+ if (ret)
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+ goto failed_set;
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+
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+ ret = clk_set_parent(cpu_root, osc);
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+ if (ret)
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+ goto failed_set;
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+
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+ ret = clk_set_rate(pllclk, 1500000000);
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+ if (ret)
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+ goto failed_set;
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+
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+ ret = clk_set_parent(cpu_root, pllclk);
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+
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+failed_set:
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+ clk_put(pllclk);
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+ clk_put(osc);
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+ }
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+
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+ return ret;
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}
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static const struct of_device_id jh7110_syscrg_match[] = {
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