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cd96cdaa60
Refreshed all patches. Compile-tested on: ar71xx, cns3xxx, imx6, x86_64 Runtime-tested on: ar71xx, cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
110 lines
2.9 KiB
Diff
110 lines
2.9 KiB
Diff
From f395a149fbbc190afbadbdcf9ce95f85f78da22f Mon Sep 17 00:00:00 2001
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From: RogerCC Lin <rogercc.lin@mediatek.com>
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Date: Thu, 30 Nov 2017 22:10:45 +0800
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Subject: [PATCH 167/224] mtd: nand: mtk: Support MT7622 NAND flash controller.
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Add tables to support MT7622 NAND flash controller.
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Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com>
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Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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---
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drivers/mtd/nand/mtk_ecc.c | 26 ++++++++++++++++++++++++++
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drivers/mtd/nand/mtk_nand.c | 16 ++++++++++++++++
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2 files changed, 42 insertions(+)
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--- a/drivers/mtd/nand/mtk_ecc.c
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+++ b/drivers/mtd/nand/mtk_ecc.c
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@@ -83,6 +83,10 @@ static const u8 ecc_strength_mt2712[] =
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40, 44, 48, 52, 56, 60, 68, 72, 80
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};
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+static const u8 ecc_strength_mt7622[] = {
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+ 4, 6, 8, 10, 12, 14, 16
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+};
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+
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enum mtk_ecc_regs {
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ECC_ENCPAR00,
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ECC_ENCIRQ_EN,
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@@ -110,6 +114,15 @@ static int mt2712_ecc_regs[] = {
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[ECC_DECIRQ_STA] = 0x204,
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};
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+static int mt7622_ecc_regs[] = {
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+ [ECC_ENCPAR00] = 0x10,
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+ [ECC_ENCIRQ_EN] = 0x30,
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+ [ECC_ENCIRQ_STA] = 0x34,
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+ [ECC_DECDONE] = 0x11c,
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+ [ECC_DECIRQ_EN] = 0x140,
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+ [ECC_DECIRQ_STA] = 0x144,
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+};
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+
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static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
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enum mtk_ecc_operation op)
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{
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@@ -458,6 +471,16 @@ static const struct mtk_ecc_caps mtk_ecc
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.pg_irq_sel = 1,
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};
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+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
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+ .err_mask = 0x3f,
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+ .ecc_strength = ecc_strength_mt7622,
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+ .ecc_regs = mt7622_ecc_regs,
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+ .num_ecc_strength = 7,
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+ .ecc_mode_shift = 4,
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+ .parity_bits = 13,
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+ .pg_irq_sel = 0,
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+};
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+
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static const struct of_device_id mtk_ecc_dt_match[] = {
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{
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.compatible = "mediatek,mt2701-ecc",
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@@ -465,6 +488,9 @@ static const struct of_device_id mtk_ecc
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}, {
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.compatible = "mediatek,mt2712-ecc",
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.data = &mtk_ecc_caps_mt2712,
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+ }, {
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+ .compatible = "mediatek,mt7622-ecc",
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+ .data = &mtk_ecc_caps_mt7622,
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},
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{},
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};
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--- a/drivers/mtd/nand/mtk_nand.c
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+++ b/drivers/mtd/nand/mtk_nand.c
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@@ -174,6 +174,10 @@ static const u8 spare_size_mt2712[] = {
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74
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};
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+static const u8 spare_size_mt7622[] = {
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+ 16, 26, 27, 28
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+};
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+
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static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
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{
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return container_of(nand, struct mtk_nfc_nand_chip, nand);
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@@ -1408,6 +1412,15 @@ static const struct mtk_nfc_caps mtk_nfc
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.max_sector_size = 1024,
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};
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+static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = {
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+ .spare_size = spare_size_mt7622,
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+ .num_spare_size = 4,
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+ .pageformat_spare_shift = 4,
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+ .nfi_clk_div = 1,
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+ .max_sector = 8,
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+ .max_sector_size = 512,
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+};
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+
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static const struct of_device_id mtk_nfc_id_table[] = {
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{
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.compatible = "mediatek,mt2701-nfc",
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@@ -1415,6 +1428,9 @@ static const struct of_device_id mtk_nfc
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}, {
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.compatible = "mediatek,mt2712-nfc",
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.data = &mtk_nfc_caps_mt2712,
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+ }, {
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+ .compatible = "mediatek,mt7622-nfc",
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+ .data = &mtk_nfc_caps_mt7622,
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},
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{}
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};
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