mirror of
https://github.com/openwrt/openwrt.git
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244 lines
7.9 KiB
Diff
244 lines
7.9 KiB
Diff
--- a/arch/arm/mach-gemini/time.c 2015-03-25 23:06:03.188317455 +0200
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+++ b/arch/arm/mach-gemini/time.c 2015-03-25 23:06:24.417315486 +0200
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@@ -15,15 +15,18 @@
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#include <asm/mach/time.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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+#include <linux/sched_clock.h>
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/*
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* Register definitions for the timers
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*/
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-#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00)
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-#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04)
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-#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08)
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-#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C)
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-#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30)
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+#define TIMER_COUNT(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x00)
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+#define TIMER_LOAD(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x04)
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+#define TIMER_MATCH1(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x08)
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+#define TIMER_MATCH2(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x0C)
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+#define TIMER_CR(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x30)
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+#define TIMER_INTR_STATE(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x34)
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+#define TIMER_INTR_MASK(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x38)
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#define TIMER_1_CR_ENABLE (1 << 0)
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#define TIMER_1_CR_CLOCK (1 << 1)
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@@ -34,27 +37,38 @@
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#define TIMER_3_CR_ENABLE (1 << 6)
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#define TIMER_3_CR_CLOCK (1 << 7)
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#define TIMER_3_CR_INT (1 << 8)
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+#define TIMER_1_CR_UPDOWN (1 << 9)
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+#define TIMER_2_CR_UPDOWN (1 << 10)
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+#define TIMER_3_CR_UPDOWN (1 << 11)
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+
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+#define TIMER_1_INT_MATCH1 (1 << 0)
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+#define TIMER_1_INT_MATCH2 (1 << 1)
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+#define TIMER_1_INT_OVERFLOW (1 << 2)
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+#define TIMER_2_INT_MATCH1 (1 << 3)
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+#define TIMER_2_INT_MATCH2 (1 << 4)
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+#define TIMER_2_INT_OVERFLOW (1 << 5)
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+#define TIMER_3_INT_MATCH1 (1 << 6)
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+#define TIMER_3_INT_MATCH2 (1 << 7)
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+#define TIMER_3_INT_OVERFLOW (1 << 8)
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+#define TIMER_INT_ALL_MASK 0x1ff
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static unsigned int tick_rate;
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+static u64 notrace gemini_read_sched_clock(void)
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+{
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+ return readl(TIMER_COUNT(GEMINI_TIMER3_BASE));
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+}
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+
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static int gemini_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 cr;
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- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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-
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- /* This may be overdoing it, feel free to test without this */
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- cr &= ~TIMER_2_CR_ENABLE;
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- cr &= ~TIMER_2_CR_INT;
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- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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-
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- /* Set next event */
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- writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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- writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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- cr |= TIMER_2_CR_ENABLE;
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- cr |= TIMER_2_CR_INT;
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- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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+ /* Setup the match register */
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+ cr = readl(TIMER_COUNT(GEMINI_TIMER1_BASE));
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+ writel(cr + cycles, TIMER_MATCH1(GEMINI_TIMER1_BASE));
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+ if (readl(TIMER_COUNT(GEMINI_TIMER1_BASE)) - cr > cycles)
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+ return -ETIME;
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return 0;
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}
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@@ -66,48 +80,68 @@
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u32 cr;
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switch (mode) {
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- case CLOCK_EVT_MODE_PERIODIC:
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- /* Start the timer */
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- writel(period,
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- TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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- writel(period,
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- TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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- cr |= TIMER_2_CR_ENABLE;
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- cr |= TIMER_2_CR_INT;
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- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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+ case CLOCK_EVT_MODE_PERIODIC:
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+ /* Stop timer and interrupt. */
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+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
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+ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
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+
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+ /* Setup timer to fire at 1/HZ intervals. */
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+ cr = 0xffffffff - (period - 1);
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+ writel(cr, TIMER_COUNT(GEMINI_TIMER1_BASE));
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+ writel(cr, TIMER_LOAD(GEMINI_TIMER1_BASE));
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+
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+ /* enable interrupt on overflaw */
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+ cr = readl(TIMER_INTR_MASK(GEMINI_TIMER_BASE));
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+ cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
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+ cr |= TIMER_1_INT_OVERFLOW;
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+ writel(cr, TIMER_INTR_MASK(GEMINI_TIMER_BASE));
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+
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+ /* start the timer */
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+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
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+ cr |= TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
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+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
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break;
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+
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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- case CLOCK_EVT_MODE_SHUTDOWN:
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+ case CLOCK_EVT_MODE_SHUTDOWN:
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+ /* Stop timer and interrupt. */
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+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
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+ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
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+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
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+
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+ /* Setup counter start from 0 */
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+ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE));
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+ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE));
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+
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+ /* enable interrupt */
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+ cr = readl(TIMER_INTR_MASK(GEMINI_TIMER_BASE));
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+ cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
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+ cr |= TIMER_1_INT_MATCH1;
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+ writel(cr, TIMER_INTR_MASK(GEMINI_TIMER_BASE));
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+
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+ /* start the timer */
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+ cr = readl(TIMER_CR(GEMINI_TIMER_BASE));
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+ cr |= TIMER_1_CR_ENABLE;
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+ writel(cr, TIMER_CR(GEMINI_TIMER_BASE));
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+ break;
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+
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case CLOCK_EVT_MODE_RESUME:
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- /*
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- * Disable also for oneshot: the set_next() call will
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- * arm the timer instead.
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- */
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- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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- cr &= ~TIMER_2_CR_ENABLE;
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- cr &= ~TIMER_2_CR_INT;
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- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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break;
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- default:
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- break;
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}
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}
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-/* Use TIMER2 as clock event */
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static struct clock_event_device gemini_clockevent = {
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- .name = "TIMER2",
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- .rating = 300, /* Reasonably fast and accurate clock event */
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- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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- .set_next_event = gemini_timer_set_next_event,
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- .set_mode = gemini_timer_set_mode,
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+ .name = "gemini_timer_1",
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+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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+ .shift = 32,
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+ .rating = 300,
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+ .set_next_event = gemini_timer_set_next_event,
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+ .set_mode = gemini_timer_set_mode,
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};
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-/*
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- * IRQ handler for the timer
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- */
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-static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id)
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+static irqreturn_t gemini_timer_intr(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &gemini_clockevent;
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@@ -116,14 +150,11 @@
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}
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static struct irqaction gemini_timer_irq = {
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- .name = "Gemini Timer Tick",
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- .flags = IRQF_TIMER,
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- .handler = gemini_timer_interrupt,
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+ .name = "gemini timer 1",
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+ .flags = IRQF_DISABLED | IRQF_TIMER,
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+ .handler = gemini_timer_intr,
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};
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-/*
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- * Set up timer interrupt, and return the current time in seconds.
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- */
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void __init gemini_timer_init(void)
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{
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u32 reg_v;
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@@ -151,20 +182,35 @@
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}
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/*
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- * Make irqs happen for the system timer
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+ * Reset the interrupt mask and status
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*/
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- setup_irq(IRQ_TIMER2, &gemini_timer_irq);
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+ writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK(GEMINI_TIMER_BASE));
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+ writel(0, TIMER_INTR_STATE(GEMINI_TIMER_BASE));
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+ writel(TIMER_1_CR_UPDOWN | TIMER_3_CR_ENABLE | TIMER_3_CR_UPDOWN,
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+ TIMER_CR(GEMINI_TIMER_BASE));
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- /* Enable and use TIMER1 as clock source */
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- writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)));
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- writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE)));
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- writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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- if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)),
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- "TIMER1", tick_rate, 300, 32,
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- clocksource_mmio_readl_up))
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- pr_err("timer: failed to initialize gemini clock source\n");
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+ /*
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+ * Setup free-running clocksource timer (interrupts
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+ * disabled.)
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+ */
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+ writel(0, TIMER_COUNT(GEMINI_TIMER3_BASE));
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+ writel(0, TIMER_LOAD(GEMINI_TIMER3_BASE));
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+ writel(0, TIMER_MATCH1(GEMINI_TIMER3_BASE));
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+ writel(0, TIMER_MATCH2(GEMINI_TIMER3_BASE));
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+ clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER3_BASE),
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+ "gemini_clocksource", tick_rate,
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+ 300, 32, clocksource_mmio_readl_up);
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+ sched_clock_register(gemini_read_sched_clock, 32, tick_rate);
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- /* Configure and register the clockevent */
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+ /*
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+ * Setup clockevent timer (interrupt-driven.)
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+ */
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+ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE));
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+ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE));
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+ writel(0, TIMER_MATCH1(GEMINI_TIMER1_BASE));
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+ writel(0, TIMER_MATCH2(GEMINI_TIMER1_BASE));
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+ setup_irq(IRQ_TIMER1, &gemini_timer_irq);
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+ gemini_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&gemini_clockevent, tick_rate,
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1, 0xffffffff);
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}
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