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c05048b0bb
This adds support for the oxnas target in U-Boot 2014.04 History can be found at https://github.com/kref/u-boot-oxnas up to 2013.10 changes from 2013.10 to 2014.04 can be followed at https://gitorious.org/openwrt-oxnas Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43389
478 lines
14 KiB
C
Executable File
478 lines
14 KiB
C
Executable File
/*******************************************************************
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*
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* File: ddr_oxsemi.c
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*
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* Description: Declarations for DDR routines and data objects
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*
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* Author: Julien Margetts
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*
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* Copyright: Oxford Semiconductor Ltd, 2009
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include "ddr.h"
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typedef unsigned int UINT;
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// DDR TIMING PARAMETERS
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typedef struct {
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unsigned int holdoff_cmd_A;
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unsigned int holdoff_cmd_ARW;
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unsigned int holdoff_cmd_N;
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unsigned int holdoff_cmd_LM;
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unsigned int holdoff_cmd_R;
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unsigned int holdoff_cmd_W;
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unsigned int holdoff_cmd_PC;
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unsigned int holdoff_cmd_RF;
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unsigned int holdoff_bank_R;
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unsigned int holdoff_bank_W;
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unsigned int holdoff_dir_RW;
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unsigned int holdoff_dir_WR;
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unsigned int holdoff_FAW;
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unsigned int latency_CAS;
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unsigned int latency_WL;
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unsigned int recovery_WR;
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unsigned int width_update;
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unsigned int odt_offset;
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unsigned int odt_drive_all;
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unsigned int use_fixed_re;
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unsigned int delay_wr_to_re;
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unsigned int wr_slave_ratio;
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unsigned int rd_slave_ratio0;
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unsigned int rd_slave_ratio1;
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} T_DDR_TIMING_PARAMETERS;
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// DDR CONFIG PARAMETERS
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typedef struct {
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unsigned int ddr_mode;
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unsigned int width;
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unsigned int blocs;
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unsigned int banks8;
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unsigned int rams;
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unsigned int asize;
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unsigned int speed;
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unsigned int cmd_mode_wr_cl_bl;
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} T_DDR_CONFIG_PARAMETERS;
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//cmd_mode_wr_cl_bl
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//when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
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//else cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
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// cmd_ bank_ dir_ lat_ rec_ width_ odt_ odt_ fix delay ratio
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// A F C update offset all re re_to_we w r0 r1
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// R L P R R W A A W W
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//Timing Parameters A W N M R W C F R W W R W S L R
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static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4,
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5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device.
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static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4,
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5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 };
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static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4,
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4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts)
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// D B B R A S
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// D W L K A S P
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//Config Parameters R D C 8 M Z D CMD_MODE
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//static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte
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static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64,
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25, 0x80200A53 }; // 128 MByte
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static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128,
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25, 0x80200A63 }; // 256 MByte
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static void ddr_phy_poll_until_locked(void)
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{
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volatile UINT reg_tmp = 0;
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volatile UINT locked = 0;
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//Extra read to put in delay before starting to poll...
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reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
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//POLL C_DDR_PHY2_REG register until clock and flock
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//!!! Ideally have a timeout on this.
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while (locked == 0) {
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reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
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//locked when bits 30 and 31 are set
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if (reg_tmp & 0xC0000000) {
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locked = 1;
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}
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}
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}
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static void ddr_poll_until_not_busy(void)
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{
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volatile UINT reg_tmp = 0;
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volatile UINT busy = 1;
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//Extra read to put in delay before starting to poll...
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reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
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//POLL DDR_STAT register until no longer busy
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//!!! Ideally have a timeout on this.
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while (busy == 1) {
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reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
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//when bit 31 is clear - core is no longer busy
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if ((reg_tmp & 0x80000000) == 0x00000000) {
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busy = 0;
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}
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}
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}
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static void ddr_issue_command(int commmand)
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{
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*(volatile UINT *) C_DDR_CMD_REG = commmand;
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ddr_poll_until_not_busy();
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}
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static void ddr_timing_initialisation(
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const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters)
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{
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volatile UINT reg_tmp = 0;
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/* update the DDR controller registers for timing parameters */
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reg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24);
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*(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp;
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reg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28);
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*(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp;
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reg_tmp = (ddr_timing_parameters->latency_CAS << 0);
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reg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4);
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reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8);
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reg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16);
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reg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21);
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reg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24);
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*(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp;
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/* Program the timing parameters in the PHY too */
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reg_tmp = (ddr_timing_parameters->use_fixed_re << 16)
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| (ddr_timing_parameters->delay_wr_to_re << 8)
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| (ddr_timing_parameters->latency_WL << 4)
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| (ddr_timing_parameters->latency_CAS << 0);
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*(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp;
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reg_tmp = ddr_timing_parameters->wr_slave_ratio;
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*(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp;
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reg_tmp = ddr_timing_parameters->rd_slave_ratio0;
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reg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8;
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*(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp;
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}
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static void ddr_normal_initialisation(
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const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz)
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{
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int i;
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volatile UINT tmp = 0;
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volatile UINT reg_tmp = 0;
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volatile UINT emr_cmd = 0;
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UINT refresh;
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//Total size of memory in Mbits...
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tmp = ddr_config_parameters->rams * ddr_config_parameters->asize
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* ddr_config_parameters->width;
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//Deduce value to program into DDR_CFG register...
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switch (tmp) {
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case 16:
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reg_tmp = 0x00020000 * 1;
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break;
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case 32:
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reg_tmp = 0x00020000 * 2;
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break;
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case 64:
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reg_tmp = 0x00020000 * 3;
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break;
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case 128:
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reg_tmp = 0x00020000 * 4;
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break;
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case 256:
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reg_tmp = 0x00020000 * 5;
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break;
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case 512:
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reg_tmp = 0x00020000 * 6;
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break;
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case 1024:
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reg_tmp = 0x00020000 * 7;
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break;
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case 2048:
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reg_tmp = 0x00020000 * 8;
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break;
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default:
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reg_tmp = 0; //forces sims not to work if badly configured
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}
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//Memory width
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tmp = ddr_config_parameters->rams * ddr_config_parameters->width;
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switch (tmp) {
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case 8:
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reg_tmp = reg_tmp + 0x00400000;
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break;
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case 16:
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reg_tmp = reg_tmp + 0x00200000;
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break;
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case 32:
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reg_tmp = reg_tmp + 0x00000000;
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break;
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default:
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reg_tmp = 0; //forces sims not to work if badly configured
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}
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//Setup DDR Mode
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switch (ddr_config_parameters->ddr_mode) {
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case 0:
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reg_tmp = reg_tmp + 0x00000000;
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break; //SDR
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case 1:
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reg_tmp = reg_tmp + 0x40000000;
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break; //DDR
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case 2:
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reg_tmp = reg_tmp + 0x80000000;
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break; //DDR2
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default:
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reg_tmp = 0; //forces sims not to work if badly configured
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}
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//Setup Banks
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if (ddr_config_parameters->banks8 == 1) {
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reg_tmp = reg_tmp + 0x00800000;
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}
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//Program DDR_CFG register...
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*(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
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//Configure PHY0 reg - se_mode is bit 1,
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//needs to be 1 for DDR (single_ended drive)
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switch (ddr_config_parameters->ddr_mode) {
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case 0:
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reg_tmp = 2 + (0 << 4);
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break; //SDR
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case 1:
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reg_tmp = 2 + (4 << 4);
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break; //DDR
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case 2:
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reg_tmp = 0 + (4 << 4);
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break; //DDR2
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default:
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reg_tmp = 0;
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}
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//Program DDR_PHY0 register...
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*(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp;
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//Read DDR_PHY* registers to exercise paths for vcd
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reg_tmp = *(volatile UINT *) C_DDR_REG_PHY3;
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reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;
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reg_tmp = *(volatile UINT *) C_DDR_REG_PHY1;
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reg_tmp = *(volatile UINT *) C_DDR_REG_PHY0;
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//Start up sequences - Different dependant on DDR mode
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switch (ddr_config_parameters->ddr_mode) {
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case 2: //DDR2
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//Start-up sequence: follows procedure described in Micron datasheet.
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//start up DDR PHY DLL
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reg_tmp = 0x00022828; // dll on, start point and inc = h28
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*(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
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reg_tmp = 0x00032828; // start on, dll on, start point and inc = h28
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*(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
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ddr_phy_poll_until_locked();
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udelay(200); //200us
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//Startup SDRAM...
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//!!! Software: CK should be running for 200us before wake-up
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ddr_issue_command( C_CMD_WAKE_UP);
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ddr_issue_command( C_CMD_NOP);
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ddr_issue_command( C_CMD_PRECHARGE_ALL);
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ddr_issue_command( C_CMD_DDR2_EMR2);
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ddr_issue_command( C_CMD_DDR2_EMR3);
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emr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE
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+ C_CMD_ENABLE_DLL;
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ddr_issue_command(emr_cmd);
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//Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation...
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udelay(1); //1us
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ddr_issue_command(
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ddr_config_parameters->cmd_mode_wr_cl_bl
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+ C_CMD_RESET_DLL);
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udelay(1); //1us
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//!!! Software: Wait 200 CK cycles before...
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//for(i=1; i<=2; i++) {
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ddr_issue_command(C_CMD_PRECHARGE_ALL);
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// !!! Software: Wait here at least 8 CK cycles
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//}
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//need a wait here to ensure PHY DLL lock before the refresh is issued
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udelay(1); //1us
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for (i = 1; i <= 2; i++) {
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ddr_issue_command( C_CMD_AUTO_REFRESH);
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//!!! Software: Wait here at least 8 CK cycles to satify tRFC
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udelay(1); //1us
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}
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//As before but without 'RESET_DLL' bit set...
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ddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl);
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udelay(1); //1us
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// OCD commands
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ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT);
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ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT);
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break;
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default:
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break; //Do nothing
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}
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//Enable auto-refresh
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// 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us
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// We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles
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// Our core now does 8 refreshes in a go, so we multiply this period by 8
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refresh = (64000 * mhz) / 8192; // Refresh period in clocks
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reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
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#ifdef BURST_REFRESH_ENABLE
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reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8);
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reg_tmp |= C_CFG_BURST_REFRESH_ENABLE;
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#else
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reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1);
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reg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE;
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#endif
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*(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
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//Verify register contents
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reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
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//printf("Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX");
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//TBD Check_data (read_data, dll_reg, "Error: bad C_DDR_PHY2_REG read", tb_pass);
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reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
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//TBD Check_data (read_data, cfg_reg, "Error: bad DDR_CFG read", tb_pass);
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//disable optimised wrapping
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if (ddr_config_parameters->ddr_mode == 2) {
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reg_tmp = 0xFFFF0000;
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*(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp;
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}
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//enable midbuffer followon
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reg_tmp = *(volatile UINT *) C_DDR_ARB_REG; // read
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reg_tmp = 0xFFFF0000 | reg_tmp;
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*(volatile UINT *) C_DDR_ARB_REG = reg_tmp;
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// Enable write behind coherency checking for all clients
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reg_tmp = 0xFFFF0000;
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*(volatile UINT *) C_DDR_AHB4_REG = reg_tmp;
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//Wait for 200 clock cycles for SDRAM DLL to lock...
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udelay(1); //1us
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}
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// Function used to Setup DDR core
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void ddr_setup(int mhz)
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{
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static const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters =
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&C_TP_DDR2_25_CL6_1GB;
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static const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters =
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&C_CP_DDR2_25_CL6;
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//Bring core out of Reset
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*(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON;
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//DDR TIMING INITIALISTION
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ddr_timing_initialisation(ddr_timing_parameters);
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//DDR NORMAL INITIALISATION
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ddr_normal_initialisation(ddr_config_parameters, mhz);
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// route all writes through one client
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*(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0
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<< DDR_ROUTE_CPU0_INSTR_SHIFT)
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| (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT)
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| (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT)
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| (2 << DDR_ROUTE_CPU1_INSTR_SHIFT)
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| (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT)
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| (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT);
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//Bring all clients out of reset
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*(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF;
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}
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void set_ddr_timing(unsigned int w, unsigned int i)
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{
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unsigned int reg;
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unsigned int wnow = 16;
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unsigned int inow = 32;
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/* reset all timing controls to known value (31) */
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writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
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writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK,
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DDR_PHY_TIMING);
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writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
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/* step up or down read delay to the requested value */
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while (wnow != w) {
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if (wnow < w) {
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reg = DDR_PHY_TIMING_INC;
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wnow++;
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} else {
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reg = 0;
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wnow--;
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}
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writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
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writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg,
|
|
DDR_PHY_TIMING);
|
|
writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
|
|
}
|
|
|
|
/* now write delay */
|
|
while (inow != i) {
|
|
if (inow < i) {
|
|
reg = DDR_PHY_TIMING_INC;
|
|
inow++;
|
|
} else {
|
|
reg = 0;
|
|
inow--;
|
|
}
|
|
writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
|
|
writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg,
|
|
DDR_PHY_TIMING);
|
|
writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
|
|
}
|
|
}
|
|
|
|
//Function used to Setup SDRAM in DDR/SDR mode
|
|
void init_ddr(int mhz)
|
|
{
|
|
/* start clocks */
|
|
enable_clock(SYS_CTRL_CLK_DDRPHY);
|
|
enable_clock(SYS_CTRL_CLK_DDR);
|
|
enable_clock(SYS_CTRL_CLK_DDRCK);
|
|
|
|
/* bring phy and core out of reset */
|
|
reset_block(SYS_CTRL_RST_DDR_PHY, 0);
|
|
reset_block(SYS_CTRL_RST_DDR, 0);
|
|
|
|
/* DDR runs at half the speed of the CPU */
|
|
ddr_setup(mhz >> 1);
|
|
return;
|
|
}
|