mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
d9386dc8e9
Drop backported patches already included in 6.6 and refresh the rest to apply. Signed-off-by: Robert Marko <robimarko@gmail.com>
46 lines
1.3 KiB
Diff
46 lines
1.3 KiB
Diff
From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
|
|
From: Mantas Pucka <mantas@8devices.com>
|
|
Date: Mon, 24 Apr 2023 15:13:32 +0300
|
|
Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
|
|
|
|
IPQ6018 has one SD/eMMC controller, add node for it.
|
|
|
|
Signed-off-by: Mantas Pucka <mantas@8devices.com>
|
|
Tested-by: Robert Marko <robimarko@gmail.com>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
|
|
1 file changed, 23 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
|
|
@@ -470,6 +470,29 @@
|
|
};
|
|
};
|
|
|
|
+ sdhc_1: mmc@7804000 {
|
|
+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
|
|
+ reg = <0x0 0x07804000 0x0 0x1000>,
|
|
+ <0x0 0x07805000 0x0 0x1000>,
|
|
+ <0x0 0x07808000 0x0 0x2000>;
|
|
+ reg-names = "hc", "cqhci", "ice";
|
|
+
|
|
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "hc_irq", "pwr_irq";
|
|
+
|
|
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
+ <&gcc GCC_SDCC1_APPS_CLK>,
|
|
+ <&xo>,
|
|
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
|
+ clock-names = "iface", "core", "xo", "ice";
|
|
+
|
|
+ resets = <&gcc GCC_SDCC1_BCR>;
|
|
+ supports-cqe;
|
|
+ bus-width = <8>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
blsp_dma: dma-controller@7884000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0x0 0x07884000 0x0 0x2b000>;
|