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https://github.com/openwrt/openwrt.git
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95d3d353f8
Copy patches from patches-6.1 to patches-6.6. No changes. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
114 lines
3.3 KiB
Diff
114 lines
3.3 KiB
Diff
From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Sun, 19 Nov 2023 22:24:16 +0100
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Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
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to DT schema
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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DT schema helps validating DTS files. Binding was moved to clock/ as
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this hardware is a clock provider. Example required a small fix for
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"reg" value (1 address cell + 1 size cell).
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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.../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
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.../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++
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2 files changed, 54 insertions(+), 29 deletions(-)
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delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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+++ /dev/null
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@@ -1,29 +0,0 @@
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-Mediatek ethsys controller
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-============================
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-
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-The Mediatek ethsys controller provides various clocks to the system.
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-
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-Required Properties:
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-
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-- compatible: Should be:
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- - "mediatek,mt2701-ethsys", "syscon"
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- - "mediatek,mt7622-ethsys", "syscon"
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- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
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- - "mediatek,mt7629-ethsys", "syscon"
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- - "mediatek,mt7981-ethsys", "syscon"
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- - "mediatek,mt7986-ethsys", "syscon"
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-- #clock-cells: Must be 1
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-- #reset-cells: Must be 1
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-
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-The ethsys controller uses the common clk binding from
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-Documentation/devicetree/bindings/clock/clock-bindings.txt
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-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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-
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-Example:
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-
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-ethsys: clock-controller@1b000000 {
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- compatible = "mediatek,mt2701-ethsys", "syscon";
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- reg = <0 0x1b000000 0 0x1000>;
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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-};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
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@@ -0,0 +1,54 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Mediatek ethsys controller
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+
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+description:
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+ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+
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+maintainers:
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+ - James Liao <jamesjj.liao@mediatek.com>
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+
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+properties:
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+ compatible:
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+ oneOf:
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+ - items:
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+ - enum:
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+ - mediatek,mt2701-ethsys
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+ - mediatek,mt7622-ethsys
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+ - mediatek,mt7629-ethsys
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+ - mediatek,mt7981-ethsys
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+ - mediatek,mt7986-ethsys
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+ - const: syscon
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+ - items:
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+ - const: mediatek,mt7623-ethsys
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+ - const: mediatek,mt2701-ethsys
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+ - const: syscon
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+
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+ reg:
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+ maxItems: 1
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+
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+ "#clock-cells":
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+ const: 1
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+
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+ "#reset-cells":
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+ const: 1
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+
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+required:
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+ - reg
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+ - "#clock-cells"
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+ - "#reset-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ clock-controller@1b000000 {
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+ compatible = "mediatek,mt2701-ethsys", "syscon";
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+ reg = <0x1b000000 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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