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895f30e31a
Mass production units will get 16 assigned MAC addresses. This allows each phy to spawn up to 7 VAPs which will each have unique MAC without needing the private bit. Signed-off-by: John Crispin <john@phrozen.org>
467 lines
7.9 KiB
Plaintext
467 lines
7.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include "mt7981.dtsi"
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/ {
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model = "OpenWrt One";
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compatible = "openwrt,one", "mediatek,mt7981";
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aliases {
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ethernet0 = &gmac1;
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label-mac-device = &gmac0;
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led-boot = &led_status_white;
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led-failsafe = &led_status_red;
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led-running = &led_status_green;
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led-upgrade = &led_status_green;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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rootdisk = <&ubi_fit_volume>;
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};
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memory {
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reg = <0 0x40000000 0 0x40000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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gpio-keys {
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compatible = "gpio-keys";
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user {
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label = "user";
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linux,code = <BTN_0>;
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gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
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};
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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};
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};
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pwm-leds {
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compatible = "pwm-leds";
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led_status_white: led-0 {
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color = <LED_COLOR_ID_WHITE>;
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function = LED_FUNCTION_STATUS;
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pwms = <&pwm 0 10000>;
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linux,default-trigger = "pattern";
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led-pattern = <0 500 25 500>;
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};
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led_status_green: led-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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pwms = <&pwm 1 10000>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led_status_red: led-0 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_STATUS;
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gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
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};
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led-1 {
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function = LED_FUNCTION_LAN;
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color = <LED_COLOR_ID_AMBER>;
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gpios = <&pio 34 GPIO_ACTIVE_LOW>;
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};
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led-2 {
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function = LED_FUNCTION_LAN;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&pio 35 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-export {
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compatible = "gpio-export";
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gpio-0 {
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gpio-export,name = "mikrobus-reset";
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gpio-export,output = <1>;
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gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
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};
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gpio-1 {
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gpio-export,name = "watchdog-enable";
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gpio-export,output = <1>;
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gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
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};
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gpio-2 {
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gpio-export,name = "usb-enable";
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gpio-export,output = <1>;
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gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
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};
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};
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gpio-watchdog {
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compatible = "linux,wdt-gpio";
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gpios = <&pio 8 GPIO_ACTIVE_LOW>;
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hw_algo = "toggle";
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hw_margin_ms = <25000>;
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always-running;
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};
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-handle = <&phy15>;
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phy-mode = "2500base-x";
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_factory_24>;
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "gmii";
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phy-handle = <&int_gbe_phy>;
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};
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};
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&mdio_bus {
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phy15: phy@f {
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reg = <0xf>;
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airoha,pnswap-rx;
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interrupt-parent = <&pio>;
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interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
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reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <20000>;
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phy-mode = "2500base-x";
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full-duplex;
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pause;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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function = LED_FUNCTION_WAN;
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color = <LED_COLOR_ID_AMBER>;
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};
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led@1 {
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reg = <1>;
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function = LED_FUNCTION_WAN;
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color = <LED_COLOR_ID_GREEN>;
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};
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};
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};
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};
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&crypto {
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status = "okay";
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};
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&pio {
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spi0_flash_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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};
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conf-pd {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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};
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};
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spi1_flash_pins: spi1-pins {
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mux {
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function = "spi";
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groups = "spi1_1";
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};
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conf-pu {
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pins = "SPI1_CS";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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};
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conf-pd {
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pins = "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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};
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};
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spi2_flash_pins: spi2-pins {
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mux {
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function = "spi";
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groups = "spi2";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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};
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};
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i2c_pins: i2c-pins {
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mux {
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function = "i2c";
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groups = "i2c0_0";
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};
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};
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uart2_pins: uart2-pins {
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mux {
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function = "uart";
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groups = "uart2_0_tx_rx";
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};
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};
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pwm_pins: pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0_0", "pwm1_1";
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};
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};
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pcie_pins: pcie-pins {
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mux {
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function = "pcie";
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groups = "pcie_pereset";
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};
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_pins>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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status = "okay";
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rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_flash_pins>;
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cs-gpios = <0>, <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-nand";
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reg = <1>;
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spi-max-frequency = <52000000>;
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spi-cal-enable;
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spi-cal-mode = "read-data";
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spi-cal-datalen = <7>;
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spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
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spi-cal-addrlen = <5>;
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spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bl2";
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reg = <0x0 0x100000>;
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read-only;
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};
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partition@580000 {
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label = "ubi";
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reg = <0x100000 0xFF00000>;
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compatible = "linux,ubi";
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volumes {
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ubi_fit_volume: ubi-volume-fit {
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volname = "fit";
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};
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};
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};
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};
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};
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_flash_pins>;
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status = "okay";
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};
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&spi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_flash_pins>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <52000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bl2-nor";
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reg = <0x00000 0x40000>;
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};
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partition@40000 {
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label = "factory";
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reg = <0x40000 0xc0000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x1000>;
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};
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macaddr_factory_4: macaddr@4 {
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reg = <0x4 0x6>;
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compatible = "mac-base";
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#nvmem-cell-cells = <1>;
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};
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macaddr_factory_24: macaddr@24 {
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reg = <0x24 0x6>;
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compatible = "mac-base";
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};
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};
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};
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partition@100000 {
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label = "fip-nor";
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reg = <0x100000 0x80000>;
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};
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partition@180000 {
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label = "recovery";
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reg = <0x180000 0xc80000>;
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};
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};
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};
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};
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&xhci {
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phys = <&u2port0 PHY_TYPE_USB2>;
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vusb33-supply = <®_3p3v>;
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vbus-supply = <®_5v>;
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mediatek,u3p-dis-msk = <0x01>;
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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&usb_phy {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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status = "okay";
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band@0 {
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reg = <0>;
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nvmem-cells = <&macaddr_factory_4 0>;
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nvmem-cell-names = "mac-address";
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};
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band@1 {
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reg = <1>;
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nvmem-cells = <&macaddr_factory_4 7>;
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nvmem-cell-names = "mac-address";
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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status = "okay";
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};
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&sgmiisys0 {
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/delete-node/ mediatek,pnswap;
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};
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