mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
851e7f77e4
New stm32 target introduces support for stm32mp1 based devices. For now it includes an initial support of the STM32MP135F-DK device. The specifications bellow only list supported features. Specifications -------------- SOC: STM32MP135FAF7 RAM: 512 MiB Storage: SD Card Ethernet: 2x 100 Mbps Wireless: 2.4GHz Cypress CYW43455 (802.11b/g/n) LEDs: Heartbeat (Blue) Buttons: 1x Reset, 1x User (USER2) USB: 4x 2.0 Type-A Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://github.com/openwrt/openwrt/pull/16716 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
109 lines
2.9 KiB
Diff
109 lines
2.9 KiB
Diff
From fcf6ca2da4650d0a7a9cd62c8c72341860931159 Mon Sep 17 00:00:00 2001
|
|
From: Christophe Roullier <christophe.roullier@foss.st.com>
|
|
Date: Mon, 10 Jun 2024 10:03:07 +0200
|
|
Subject: [PATCH 4/5] ARM: dts: stm32: add ethernet1 and ethernet2 support on
|
|
stm32mp13
|
|
|
|
Both instances ethernet based on GMAC SNPS IP on stm32mp13.
|
|
GMAC IP version is SNPS 4.20.
|
|
|
|
Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
|
|
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
|
---
|
|
arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++
|
|
arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++
|
|
2 files changed, 69 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
|
|
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
|
|
@@ -883,6 +883,12 @@
|
|
ts_cal2: calib@5e {
|
|
reg = <0x5e 0x2>;
|
|
};
|
|
+ ethernet_mac1_address: mac1@e4 {
|
|
+ reg = <0xe4 0x6>;
|
|
+ };
|
|
+ ethernet_mac2_address: mac2@ea {
|
|
+ reg = <0xea 0x6>;
|
|
+ };
|
|
};
|
|
|
|
etzpc: bus@5c007000 {
|
|
@@ -1409,6 +1415,38 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ ethernet1: ethernet@5800a000 {
|
|
+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
|
|
+ reg = <0x5800a000 0x2000>;
|
|
+ reg-names = "stmmaceth";
|
|
+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <&exti 68 1>;
|
|
+ interrupt-names = "macirq", "eth_wake_irq";
|
|
+ clock-names = "stmmaceth",
|
|
+ "mac-clk-tx",
|
|
+ "mac-clk-rx",
|
|
+ "ethstp",
|
|
+ "eth-ck";
|
|
+ clocks = <&rcc ETH1MAC>,
|
|
+ <&rcc ETH1TX>,
|
|
+ <&rcc ETH1RX>,
|
|
+ <&rcc ETH1STP>,
|
|
+ <&rcc ETH1CK_K>;
|
|
+ st,syscon = <&syscfg 0x4 0xff0000>;
|
|
+ snps,mixed-burst;
|
|
+ snps,pbl = <2>;
|
|
+ snps,axi-config = <&stmmac_axi_config_1>;
|
|
+ snps,tso;
|
|
+ access-controllers = <&etzpc 48>;
|
|
+ status = "disabled";
|
|
+
|
|
+ stmmac_axi_config_1: stmmac-axi-config {
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
+ snps,rd_osr_lmt = <0x7>;
|
|
+ snps,wr_osr_lmt = <0x7>;
|
|
+ };
|
|
+ };
|
|
+
|
|
usbphyc: usbphyc@5a006000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
--- a/arch/arm/boot/dts/st/stm32mp133.dtsi
|
|
+++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
|
|
@@ -68,4 +68,35 @@
|
|
};
|
|
};
|
|
};
|
|
+
|
|
+ ethernet2: ethernet@5800e000 {
|
|
+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
|
|
+ reg = <0x5800e000 0x2000>;
|
|
+ reg-names = "stmmaceth";
|
|
+ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+ clock-names = "stmmaceth",
|
|
+ "mac-clk-tx",
|
|
+ "mac-clk-rx",
|
|
+ "ethstp",
|
|
+ "eth-ck";
|
|
+ clocks = <&rcc ETH2MAC>,
|
|
+ <&rcc ETH2TX>,
|
|
+ <&rcc ETH2RX>,
|
|
+ <&rcc ETH2STP>,
|
|
+ <&rcc ETH2CK_K>;
|
|
+ st,syscon = <&syscfg 0x4 0xff000000>;
|
|
+ snps,mixed-burst;
|
|
+ snps,pbl = <2>;
|
|
+ snps,axi-config = <&stmmac_axi_config_2>;
|
|
+ snps,tso;
|
|
+ access-controllers = <&etzpc 49>;
|
|
+ status = "disabled";
|
|
+
|
|
+ stmmac_axi_config_2: stmmac-axi-config {
|
|
+ snps,blen = <0 0 0 0 16 8 4>;
|
|
+ snps,rd_osr_lmt = <0x7>;
|
|
+ snps,wr_osr_lmt = <0x7>;
|
|
+ };
|
|
+ };
|
|
};
|