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1. Add sdhc clock for MT7620 and MT76x8 SoCs. 2. Fix clock driver warning for RT2880, RT305x and RT3883. Link: https://lore.kernel.org/all/20240910044024.120009-1-sergio.paracuellos@gmail.com/ Signed-off-by: Shiji Yang <yangshiji66@qq.com> Link: https://github.com/openwrt/openwrt/pull/17037 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
102 lines
3.9 KiB
Diff
102 lines
3.9 KiB
Diff
From 198675bbc03d437fb80a35d781ad13d622d0ff68 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Tue, 10 Sep 2024 06:40:24 +0200
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Subject: [PATCH 3/3] clk: ralink: mtmips: add mmc related clocks for SoCs
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MT7620, MT7628 and MT7688
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Original architecture clock code from where this driver was derived did not
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include nothing related to mmc clocks. OpenWRT people started to use mtk-sd
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upstream driver recently and they were forced to use a dts 'fixed-clock'
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node with 48 MHz clock:
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- https://github.com/openwrt/openwrt/pull/15896
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The proper thing to do to avoid that is to add the mmc related clocks to the
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driver to avoid a dts with fixed clocks nodes. The minimal documentation in
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the mt7620 programming guide says that there is a BBP_PLL clock of 480 MHz
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derived from the 40 MHz XTAL and from there a clock divider by ten produces
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the desired SDHC clock of 48 MHz for the mmc. Hence add a fixed clock 'bbppll'
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and factor clock 'sdhc' ten divider child to properly set the 'mmc' peripheral
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clock with the desired 48 Mhz rate.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20240910044024.120009-4-sergio.paracuellos@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/ralink/clk-mtmips.c | 30 +++++++++++++++++++++++-------
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1 file changed, 23 insertions(+), 7 deletions(-)
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--- a/drivers/clk/ralink/clk-mtmips.c
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+++ b/drivers/clk/ralink/clk-mtmips.c
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@@ -207,6 +207,7 @@ static struct mtmips_clk mt7620_pherip_c
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{ CLK_PERIPH("10000b00.spi", "bus") },
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{ CLK_PERIPH("10000b40.spi", "bus") },
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{ CLK_PERIPH("10000c00.uartlite", "periph") },
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+ { CLK_PERIPH("10130000.mmc", "sdhc") },
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{ CLK_PERIPH("10180000.wmac", "xtal") }
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};
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@@ -220,6 +221,7 @@ static struct mtmips_clk mt76x8_pherip_c
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{ CLK_PERIPH("10000c00.uart0", "periph") },
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{ CLK_PERIPH("10000d00.uart1", "periph") },
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{ CLK_PERIPH("10000e00.uart2", "periph") },
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+ { CLK_PERIPH("10130000.mmc", "sdhc") },
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{ CLK_PERIPH("10300000.wmac", "xtal") }
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};
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@@ -272,8 +274,13 @@ static struct mtmips_clk_fixed rt3352_fi
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CLK_FIXED("periph", "xtal", 40000000)
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};
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+static struct mtmips_clk_fixed mt7620_fixed_clocks[] = {
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+ CLK_FIXED("bbppll", "xtal", 480000000)
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+};
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+
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static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
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- CLK_FIXED("pcmi2s", "xtal", 480000000),
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+ CLK_FIXED("bbppll", "xtal", 480000000),
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+ CLK_FIXED("pcmi2s", "bbppll", 480000000),
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CLK_FIXED("periph", "xtal", 40000000)
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};
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@@ -328,6 +335,15 @@ static struct mtmips_clk_factor rt305x_f
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CLK_FACTOR("bus", "cpu", 1, 3)
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};
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+static struct mtmips_clk_factor mt7620_factor_clocks[] = {
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+ CLK_FACTOR("sdhc", "bbppll", 1, 10)
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+};
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+
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+static struct mtmips_clk_factor mt76x8_factor_clocks[] = {
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+ CLK_FACTOR("bus", "cpu", 1, 3),
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+ CLK_FACTOR("sdhc", "bbppll", 1, 10)
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+};
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+
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static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
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struct mtmips_clk_priv *priv)
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{
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@@ -811,10 +827,10 @@ static const struct mtmips_clk_data rt53
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static const struct mtmips_clk_data mt7620_clk_data = {
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.clk_base = mt7620_clks_base,
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.num_clk_base = ARRAY_SIZE(mt7620_clks_base),
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- .clk_fixed = NULL,
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- .num_clk_fixed = 0,
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- .clk_factor = NULL,
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- .num_clk_factor = 0,
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+ .clk_fixed = mt7620_fixed_clocks,
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+ .num_clk_fixed = ARRAY_SIZE(mt7620_fixed_clocks),
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+ .clk_factor = mt7620_factor_clocks,
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+ .num_clk_factor = ARRAY_SIZE(mt7620_factor_clocks),
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.clk_periph = mt7620_pherip_clks,
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.num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
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};
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@@ -824,8 +840,8 @@ static const struct mtmips_clk_data mt76
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.num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
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.clk_fixed = mt76x8_fixed_clocks,
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.num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
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- .clk_factor = rt305x_factor_clocks,
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- .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
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+ .clk_factor = mt76x8_factor_clocks,
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+ .num_clk_factor = ARRAY_SIZE(mt76x8_factor_clocks),
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.clk_periph = mt76x8_pherip_clks,
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.num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
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};
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