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71 lines
2.5 KiB
Diff
71 lines
2.5 KiB
Diff
From 202f1bad2707e843dccc0fb08233692f8c845f90 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 8 Mar 2012 12:00:17 +0100
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Subject: [PATCH 48/70] MIPS: lantiq: pci: rename variable inside
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* rename a global var inside the pci code
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---
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arch/mips/pci/ops-lantiq.c | 6 +++---
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arch/mips/pci/pci-lantiq.c | 6 +++---
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arch/mips/pci/pci-lantiq.h | 2 +-
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3 files changed, 7 insertions(+), 7 deletions(-)
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--- a/arch/mips/pci/ops-lantiq.c
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+++ b/arch/mips/pci/ops-lantiq.c
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@@ -41,7 +41,7 @@ static int ltq_pci_config_access(unsigne
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spin_lock_irqsave(&ebu_lock, flags);
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- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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+ cfg_base = (unsigned long) ltq_pci_cfgbase;
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cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
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LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
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@@ -55,11 +55,11 @@ static int ltq_pci_config_access(unsigne
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wmb();
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/* clean possible Master abort */
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- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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+ cfg_base = (unsigned long) ltq_pci_cfgbase;
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cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
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temp = ltq_r32(((u32 *)(cfg_base)));
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temp = swab32(temp);
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- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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+ cfg_base = (unsigned long) ltq_pci_cfgbase;
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cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
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ltq_w32(temp, ((u32 *)cfg_base));
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--- a/arch/mips/pci/pci-lantiq.c
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+++ b/arch/mips/pci/pci-lantiq.c
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@@ -65,8 +65,8 @@
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#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
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#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
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-#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
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-#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
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+#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_cfgbase + (y))
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+#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_cfgbase + (x))
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struct ltq_pci_gpio_map {
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int pin;
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@@ -273,7 +273,7 @@ static int __devinit ltq_pci_probe(struc
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pci_probe_only = 0;
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ltq_pci_irq_map = ltq_pci_data->irq;
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ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
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- ltq_pci_mapped_cfg =
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+ ltq_pci_cfgbase =
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ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
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ltq_pci_controller.io_map_base =
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(unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
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--- a/arch/mips/pci/pci-lantiq.h
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+++ b/arch/mips/pci/pci-lantiq.h
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@@ -9,7 +9,7 @@
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#ifndef _LTQ_PCI_H__
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#define _LTQ_PCI_H__
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-extern __iomem void *ltq_pci_mapped_cfg;
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+extern __iomem void *ltq_pci_cfgbase;
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extern int ltq_pci_read_config_dword(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val);
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extern int ltq_pci_write_config_dword(struct pci_bus *bus,
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