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cd634afe6c
Delete the crypto-lib-blake2s kmod package, as BLAKE2s is now built-in. Patches automatically rebased. Build system: x86_64 Build-tested: ipq806x/R7800, x86/64 Signed-off-by: John Audia <therealgraysky@proton.me>
468 lines
14 KiB
Diff
468 lines
14 KiB
Diff
From 293903b9dfe43520f01374dc1661be11d6838c49 Mon Sep 17 00:00:00 2001
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From: Sander Vanheule <sander@svanheule.net>
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Date: Thu, 18 Nov 2021 17:29:52 +0100
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Subject: watchdog: Add Realtek Otto watchdog timer
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Realtek MIPS SoCs (platform name Otto) have a watchdog timer with
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pretimeout notifitication support. The WDT can (partially) hard reset,
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or soft reset the SoC.
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This driver implements all features as described in the devicetree
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binding, except the phase2 interrupt, and also functions as a restart
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handler. The cpu reset mode is considered to be a "warm" restart, since
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this mode does not reset all peripherals. Being an embedded system
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though, the "cpu" and "software" modes will still cause the bootloader
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to run on restart.
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It is not known how a forced system reset can be disabled on the
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supported platforms. This means that the phase2 interrupt will only fire
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at the same time as reset, so implementing phase2 is of little use.
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Signed-off-by: Sander Vanheule <sander@svanheule.net>
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Reviewed-by: Guenter Roeck <linux@roeck-us.net>
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Link: https://lore.kernel.org/r/6d060bccbdcc709cfa79203485db85aad3c3beb5.1637252610.git.sander@svanheule.net
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Signed-off-by: Guenter Roeck <linux@roeck-us.net>
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---
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MAINTAINERS | 7 +
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drivers/watchdog/Kconfig | 13 ++
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drivers/watchdog/Makefile | 1 +
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drivers/watchdog/realtek_otto_wdt.c | 384 ++++++++++++++++++++++++++++++++++++
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4 files changed, 405 insertions(+)
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create mode 100644 drivers/watchdog/realtek_otto_wdt.c
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -14816,6 +14816,13 @@ S: Maintained
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F: include/sound/rt*.h
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F: sound/soc/codecs/rt*
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+REALTEK OTTO WATCHDOG
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+M: Sander Vanheule <sander@svanheule.net>
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+L: linux-watchdog@vger.kernel.org
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+S: Maintained
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+F: Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml
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+F: driver/watchdog/realtek_otto_wdt.c
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+
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REALTEK RTL83xx SMI DSA ROUTER CHIPS
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M: Linus Walleij <linus.walleij@linaro.org>
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S: Maintained
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--- a/drivers/watchdog/Kconfig
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+++ b/drivers/watchdog/Kconfig
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@@ -995,6 +995,19 @@ config RTD119X_WATCHDOG
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Say Y here to include support for the watchdog timer in
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Realtek RTD1295 SoCs.
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+config REALTEK_OTTO_WDT
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+ tristate "Realtek Otto MIPS watchdog support"
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+ depends on MACH_REALTEK_RTL || COMPILE_TEST
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+ depends on COMMON_CLK
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+ select WATCHDOG_CORE
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+ default MACH_REALTEK_RTL
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+ help
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+ Say Y here to include support for the watchdog timer on Realtek
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+ RTL838x, RTL839x, RTL930x SoCs. This watchdog has pretimeout
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+ notifications and system reset on timeout.
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+
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+ When built as a module this will be called realtek_otto_wdt.
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+
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config SPRD_WATCHDOG
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tristate "Spreadtrum watchdog support"
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depends on ARCH_SPRD || COMPILE_TEST
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--- a/drivers/watchdog/Makefile
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+++ b/drivers/watchdog/Makefile
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@@ -174,6 +174,7 @@ obj-$(CONFIG_IMGPDC_WDT) += imgpdc_wdt.o
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obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o
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obj-$(CONFIG_PIC32_WDT) += pic32-wdt.o
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obj-$(CONFIG_PIC32_DMT) += pic32-dmt.o
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+obj-$(CONFIG_REALTEK_OTTO_WDT) += realtek_otto_wdt.o
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# PARISC Architecture
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--- /dev/null
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+++ b/drivers/watchdog/realtek_otto_wdt.c
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@@ -0,0 +1,384 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+
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+/*
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+ * Realtek Otto MIPS platform watchdog
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+ *
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+ * Watchdog timer that will reset the system after timeout, using the selected
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+ * reset mode.
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+ *
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+ * Counter scaling and timeouts:
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+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
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+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
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+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
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+ * Generates an interrupt, WDT cannot be stopped after phase 1
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+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
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+ * Resets the system according to RST_MODE
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+ */
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+
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+#include <linux/bits.h>
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+#include <linux/bitfield.h>
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/math.h>
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+#include <linux/minmax.h>
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+#include <linux/module.h>
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+#include <linux/mod_devicetable.h>
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+#include <linux/platform_device.h>
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+#include <linux/property.h>
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+#include <linux/reboot.h>
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+#include <linux/watchdog.h>
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+
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+#define OTTO_WDT_REG_CNTR 0x0
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+#define OTTO_WDT_CNTR_PING BIT(31)
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+
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+#define OTTO_WDT_REG_INTR 0x4
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+#define OTTO_WDT_INTR_PHASE_1 BIT(31)
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+#define OTTO_WDT_INTR_PHASE_2 BIT(30)
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+
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+#define OTTO_WDT_REG_CTRL 0x8
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+#define OTTO_WDT_CTRL_ENABLE BIT(31)
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+#define OTTO_WDT_CTRL_PRESCALE GENMASK(30, 29)
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+#define OTTO_WDT_CTRL_PHASE1 GENMASK(26, 22)
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+#define OTTO_WDT_CTRL_PHASE2 GENMASK(19, 15)
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+#define OTTO_WDT_CTRL_RST_MODE GENMASK(1, 0)
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+#define OTTO_WDT_MODE_SOC 0
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+#define OTTO_WDT_MODE_CPU 1
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+#define OTTO_WDT_MODE_SOFTWARE 2
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+#define OTTO_WDT_CTRL_DEFAULT OTTO_WDT_MODE_CPU
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+
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+#define OTTO_WDT_PRESCALE_MAX 3
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+
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+/*
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+ * One higher than the max values contained in PHASE{1,2}, since a value of 0
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+ * corresponds to one tick.
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+ */
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+#define OTTO_WDT_PHASE_TICKS_MAX 32
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+
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+/*
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+ * The maximum reset delay is actually 2×32 ticks, but that would require large
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+ * pretimeout values for timeouts longer than 32 ticks. Limit the maximum timeout
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+ * to 32 + 1 to ensure small pretimeout values can be configured as expected.
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+ */
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+#define OTTO_WDT_TIMEOUT_TICKS_MAX (OTTO_WDT_PHASE_TICKS_MAX + 1)
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+
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+struct otto_wdt_ctrl {
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+ struct watchdog_device wdev;
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+ struct device *dev;
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+ void __iomem *base;
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+ unsigned int clk_rate_khz;
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+ int irq_phase1;
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+};
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+
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+static int otto_wdt_start(struct watchdog_device *wdev)
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+{
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+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
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+ u32 v;
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+
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+ v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
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+ v |= OTTO_WDT_CTRL_ENABLE;
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+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
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+
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+ return 0;
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+}
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+
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+static int otto_wdt_stop(struct watchdog_device *wdev)
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+{
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+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
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+ u32 v;
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+
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+ v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
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+ v &= ~OTTO_WDT_CTRL_ENABLE;
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+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
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+
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+ return 0;
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+}
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+
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+static int otto_wdt_ping(struct watchdog_device *wdev)
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+{
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+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
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+
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+ iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR);
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+
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+ return 0;
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+}
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+
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+static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)
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+{
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+ return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz);
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+}
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+
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+/*
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+ * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds
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+ * the value stored in those fields. This means each phase will run for at least
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+ * one tick, so small values need to be clamped to correctly reflect the timeout.
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+ */
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+static inline unsigned int div_round_ticks(unsigned int val, unsigned int tick_duration,
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+ unsigned int min_ticks)
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+{
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+ return max(min_ticks, DIV_ROUND_UP(val, tick_duration));
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+}
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+
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+static int otto_wdt_determine_timeouts(struct watchdog_device *wdev, unsigned int timeout,
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+ unsigned int pretimeout)
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+{
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+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
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+ unsigned int pretimeout_ms = pretimeout * 1000;
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+ unsigned int timeout_ms = timeout * 1000;
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+ unsigned int prescale_next = 0;
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+ unsigned int phase1_ticks;
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+ unsigned int phase2_ticks;
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+ unsigned int total_ticks;
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+ unsigned int prescale;
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+ unsigned int tick_ms;
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+ u32 v;
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+
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+ do {
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+ prescale = prescale_next;
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+ if (prescale > OTTO_WDT_PRESCALE_MAX)
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+ return -EINVAL;
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+
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+ tick_ms = otto_wdt_tick_ms(ctrl, prescale);
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+ total_ticks = div_round_ticks(timeout_ms, tick_ms, 2);
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+ phase1_ticks = div_round_ticks(timeout_ms - pretimeout_ms, tick_ms, 1);
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+ phase2_ticks = total_ticks - phase1_ticks;
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+
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+ prescale_next++;
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+ } while (phase1_ticks > OTTO_WDT_PHASE_TICKS_MAX
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+ || phase2_ticks > OTTO_WDT_PHASE_TICKS_MAX);
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+
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+ v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
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+
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+ v &= ~(OTTO_WDT_CTRL_PRESCALE | OTTO_WDT_CTRL_PHASE1 | OTTO_WDT_CTRL_PHASE2);
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+ v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE1, phase1_ticks - 1);
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+ v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE2, phase2_ticks - 1);
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+ v |= FIELD_PREP(OTTO_WDT_CTRL_PRESCALE, prescale);
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+
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+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
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+
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+ timeout_ms = total_ticks * tick_ms;
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+ ctrl->wdev.timeout = timeout_ms / 1000;
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+
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+ pretimeout_ms = phase2_ticks * tick_ms;
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+ ctrl->wdev.pretimeout = pretimeout_ms / 1000;
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+
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+ return 0;
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+}
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+
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+static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val)
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+{
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+ return otto_wdt_determine_timeouts(wdev, val, min(wdev->pretimeout, val - 1));
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+}
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+
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+static int otto_wdt_set_pretimeout(struct watchdog_device *wdev, unsigned int val)
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+{
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+ return otto_wdt_determine_timeouts(wdev, wdev->timeout, val);
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+}
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+
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+static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,
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+ void *data)
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+{
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+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
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+ u32 reset_mode;
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+ u32 v;
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+
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+ disable_irq(ctrl->irq_phase1);
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+
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+ switch (reboot_mode) {
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+ case REBOOT_SOFT:
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+ reset_mode = OTTO_WDT_MODE_SOFTWARE;
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+ break;
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+ case REBOOT_WARM:
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+ reset_mode = OTTO_WDT_MODE_CPU;
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+ break;
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+ default:
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+ reset_mode = OTTO_WDT_MODE_SOC;
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+ break;
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+ }
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+
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+ /* Configure for shortest timeout and wait for reset to occur */
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+ v = FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, reset_mode) | OTTO_WDT_CTRL_ENABLE;
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+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
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+
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+ mdelay(3 * otto_wdt_tick_ms(ctrl, 0));
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+
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+ return 0;
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+}
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+
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+static irqreturn_t otto_wdt_phase1_isr(int irq, void *dev_id)
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+{
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+ struct otto_wdt_ctrl *ctrl = dev_id;
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+
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+ iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR);
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+ dev_crit(ctrl->dev, "phase 1 timeout\n");
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+ watchdog_notify_pretimeout(&ctrl->wdev);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static const struct watchdog_ops otto_wdt_ops = {
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+ .owner = THIS_MODULE,
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+ .start = otto_wdt_start,
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+ .stop = otto_wdt_stop,
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+ .ping = otto_wdt_ping,
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+ .set_timeout = otto_wdt_set_timeout,
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+ .set_pretimeout = otto_wdt_set_pretimeout,
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+ .restart = otto_wdt_restart,
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+};
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+
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+static const struct watchdog_info otto_wdt_info = {
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+ .identity = "Realtek Otto watchdog timer",
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+ .options = WDIOF_KEEPALIVEPING |
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+ WDIOF_MAGICCLOSE |
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+ WDIOF_SETTIMEOUT |
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+ WDIOF_PRETIMEOUT,
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+};
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+
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+static void otto_wdt_clock_action(void *data)
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+{
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+ clk_disable_unprepare(data);
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+}
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+
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+static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl)
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+{
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+ struct clk *clk = devm_clk_get(ctrl->dev, NULL);
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+ int ret;
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+
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+ if (IS_ERR(clk))
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+ return dev_err_probe(ctrl->dev, PTR_ERR(clk), "Failed to get clock\n");
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+
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+ ret = clk_prepare_enable(clk);
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+ if (ret)
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+ return dev_err_probe(ctrl->dev, ret, "Failed to enable clock\n");
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+
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+ ret = devm_add_action_or_reset(ctrl->dev, otto_wdt_clock_action, clk);
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+ if (ret)
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+ return ret;
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+
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+ ctrl->clk_rate_khz = clk_get_rate(clk) / 1000;
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+ if (ctrl->clk_rate_khz == 0)
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+ return dev_err_probe(ctrl->dev, -ENXIO, "Failed to get clock rate\n");
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+
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+ return 0;
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+}
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+
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+static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)
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+{
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+ static const char *mode_property = "realtek,reset-mode";
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+ const struct fwnode_handle *node = ctrl->dev->fwnode;
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+ int mode_count;
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+ u32 mode;
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+ u32 v;
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+
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+ if (!node)
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+ return -ENXIO;
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+
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+ mode_count = fwnode_property_string_array_count(node, mode_property);
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+ if (mode_count < 0)
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+ return mode_count;
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+ else if (mode_count == 0)
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+ return 0;
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+ else if (mode_count != 1)
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+ return -EINVAL;
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+
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+ if (fwnode_property_match_string(node, mode_property, "soc") == 0)
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+ mode = OTTO_WDT_MODE_SOC;
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+ else if (fwnode_property_match_string(node, mode_property, "cpu") == 0)
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+ mode = OTTO_WDT_MODE_CPU;
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+ else if (fwnode_property_match_string(node, mode_property, "software") == 0)
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+ mode = OTTO_WDT_MODE_SOFTWARE;
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+ else
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+ return -EINVAL;
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+
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+ v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
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+ v &= ~OTTO_WDT_CTRL_RST_MODE;
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+ v |= FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, mode);
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+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
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+
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+ return 0;
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+}
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+
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+static int otto_wdt_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct otto_wdt_ctrl *ctrl;
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+ unsigned int max_tick_ms;
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+ int ret;
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+
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+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
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+ if (!ctrl)
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+ return -ENOMEM;
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+
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+ ctrl->dev = dev;
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+ ctrl->base = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(ctrl->base))
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+ return PTR_ERR(ctrl->base);
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+
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+ /* Clear any old interrupts and reset initial state */
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+ iowrite32(OTTO_WDT_INTR_PHASE_1 | OTTO_WDT_INTR_PHASE_2,
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+ ctrl->base + OTTO_WDT_REG_INTR);
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+ iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);
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+
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+ ret = otto_wdt_probe_clk(ctrl);
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+ if (ret)
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+ return ret;
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+
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+ ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
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+ if (ctrl->irq_phase1 < 0)
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+ return ctrl->irq_phase1;
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+
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+ ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,
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+ "realtek-otto-wdt", ctrl);
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+ if (ret)
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+ return dev_err_probe(dev, ret, "Failed to get IRQ for phase1\n");
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+
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+ ret = otto_wdt_probe_reset_mode(ctrl);
|
||
+ if (ret)
|
||
+ return dev_err_probe(dev, ret, "Invalid reset mode specified\n");
|
||
+
|
||
+ ctrl->wdev.parent = dev;
|
||
+ ctrl->wdev.info = &otto_wdt_info;
|
||
+ ctrl->wdev.ops = &otto_wdt_ops;
|
||
+
|
||
+ /*
|
||
+ * Since pretimeout cannot be disabled, min. timeout is twice the
|
||
+ * subsystem resolution. Max. timeout is ca. 43s at a bus clock of 200MHz.
|
||
+ */
|
||
+ ctrl->wdev.min_timeout = 2;
|
||
+ max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);
|
||
+ ctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX;
|
||
+ ctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000);
|
||
+
|
||
+ watchdog_set_drvdata(&ctrl->wdev, ctrl);
|
||
+ watchdog_init_timeout(&ctrl->wdev, 0, dev);
|
||
+ watchdog_stop_on_reboot(&ctrl->wdev);
|
||
+ watchdog_set_restart_priority(&ctrl->wdev, 128);
|
||
+
|
||
+ ret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1);
|
||
+ if (ret)
|
||
+ return dev_err_probe(dev, ret, "Failed to set timeout\n");
|
||
+
|
||
+ return devm_watchdog_register_device(dev, &ctrl->wdev);
|
||
+}
|
||
+
|
||
+static const struct of_device_id otto_wdt_ids[] = {
|
||
+ { .compatible = "realtek,rtl8380-wdt" },
|
||
+ { .compatible = "realtek,rtl8390-wdt" },
|
||
+ { .compatible = "realtek,rtl9300-wdt" },
|
||
+ { }
|
||
+};
|
||
+MODULE_DEVICE_TABLE(of, otto_wdt_ids);
|
||
+
|
||
+static struct platform_driver otto_wdt_driver = {
|
||
+ .probe = otto_wdt_probe,
|
||
+ .driver = {
|
||
+ .name = "realtek-otto-watchdog",
|
||
+ .of_match_table = otto_wdt_ids,
|
||
+ },
|
||
+};
|
||
+module_platform_driver(otto_wdt_driver);
|
||
+
|
||
+MODULE_LICENSE("GPL v2");
|
||
+MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>");
|
||
+MODULE_DESCRIPTION("Realtek Otto watchdog timer driver");
|