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https://github.com/openwrt/openwrt.git
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58d2bd88ae
Changes:
- Update patches
- Update dts with new binding
Tx term offset dropped and replaced with a new compatible
Removed:
- 0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x
Pci init does the same exact thing (was needed in older kernel version)
- 0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B
Rejected upstream, can't find any reason to have this. No regression with
testing it on R7800.
Tested on R7800 (ipq8065), R7500 v2 ("ipq8064-v2")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Paul Blazejowski <paulb@blazebox.homeip.net> [R7800]
[rebase and refresh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
75 lines
2.4 KiB
Diff
75 lines
2.4 KiB
Diff
From 51ed2c2b60265006bde7531d10993cf24def0aee Mon Sep 17 00:00:00 2001
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From: Sham Muthayyan <smuthayy@codeaurora.org>
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Date: Mon, 15 Jun 2020 23:06:07 +0200
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Subject: PCI: qcom: Support pci speed set for ipq806x
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Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to
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some hardware limitations. Add support for speed setting defined by the
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max-link-speed binding. If not defined the max speed is set to GEN2 by
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default.
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Link: https://lore.kernel.org/r/20200615210608.21469-12-ansuelsmth@gmail.com
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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---
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Backported with light changes:
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* One include is missing in kernel 5.4
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drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -27,6 +27,7 @@
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#include <linux/slab.h>
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#include <linux/types.h>
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+#include "../../pci.h"
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#include "pcie-designware.h"
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#define PCIE20_PARF_SYS_CTRL 0x00
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@@ -98,6 +99,8 @@
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#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
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#define SLV_ADDR_SPACE_SZ 0x10000000
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+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
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+
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#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
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#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
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struct qcom_pcie_resources_2_1_0 {
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@@ -184,6 +187,7 @@ struct qcom_pcie {
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struct phy *phy;
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struct gpio_desc *reset;
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const struct qcom_pcie_ops *ops;
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+ int gen;
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};
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#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
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@@ -384,6 +388,11 @@ static int qcom_pcie_init_2_1_0(struct q
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/* wait for clock acquisition */
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usleep_range(1000, 1500);
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+ if (pcie->gen == 1) {
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+ val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
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+ val |= PCI_EXP_LNKSTA_CLS_2_5GB;
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+ writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
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+ }
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/* Set the Max TLP size to 2K, instead of using default of 4K */
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writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
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@@ -1248,6 +1257,10 @@ static int qcom_pcie_probe(struct platfo
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goto err_pm_runtime_put;
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}
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+ pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
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+ if (pcie->gen < 0)
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+ pcie->gen = 2;
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+
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
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pcie->parf = devm_ioremap_resource(dev, res);
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if (IS_ERR(pcie->parf)) {
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