mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
114 lines
3.5 KiB
Diff
114 lines
3.5 KiB
Diff
From ea2f40c943f4a6d39a2f3ea4660266250d37c95a Mon Sep 17 00:00:00 2001
|
|
From: Hal Feng <hal.feng@starfivetech.com>
|
|
Date: Sat, 1 Apr 2023 19:19:27 +0800
|
|
Subject: [PATCH 015/122] reset: starfive: Add StarFive JH7110 reset driver
|
|
|
|
Add auxiliary driver to support StarFive JH7110 system
|
|
and always-on resets.
|
|
|
|
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
|
|
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
|
|
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
|
|
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
---
|
|
drivers/reset/starfive/Kconfig | 8 +++
|
|
drivers/reset/starfive/Makefile | 1 +
|
|
.../reset/starfive/reset-starfive-jh7110.c | 70 +++++++++++++++++++
|
|
3 files changed, 79 insertions(+)
|
|
create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
|
|
|
|
--- a/drivers/reset/starfive/Kconfig
|
|
+++ b/drivers/reset/starfive/Kconfig
|
|
@@ -10,3 +10,11 @@ config RESET_STARFIVE_JH7100
|
|
default ARCH_STARFIVE
|
|
help
|
|
This enables the reset controller driver for the StarFive JH7100 SoC.
|
|
+
|
|
+config RESET_STARFIVE_JH7110
|
|
+ bool "StarFive JH7110 Reset Driver"
|
|
+ depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS
|
|
+ select RESET_STARFIVE_JH71X0
|
|
+ default ARCH_STARFIVE
|
|
+ help
|
|
+ This enables the reset controller driver for the StarFive JH7110 SoC.
|
|
--- a/drivers/reset/starfive/Makefile
|
|
+++ b/drivers/reset/starfive/Makefile
|
|
@@ -2,3 +2,4 @@
|
|
obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
|
|
|
|
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
|
|
+obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
|
|
--- /dev/null
|
|
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
|
|
@@ -0,0 +1,70 @@
|
|
+// SPDX-License-Identifier: GPL-2.0-or-later
|
|
+/*
|
|
+ * Reset driver for the StarFive JH7110 SoC
|
|
+ *
|
|
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
|
|
+ */
|
|
+
|
|
+#include <linux/auxiliary_bus.h>
|
|
+
|
|
+#include "reset-starfive-jh71x0.h"
|
|
+
|
|
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
|
|
+
|
|
+struct jh7110_reset_info {
|
|
+ unsigned int nr_resets;
|
|
+ unsigned int assert_offset;
|
|
+ unsigned int status_offset;
|
|
+};
|
|
+
|
|
+static const struct jh7110_reset_info jh7110_sys_info = {
|
|
+ .nr_resets = JH7110_SYSRST_END,
|
|
+ .assert_offset = 0x2F8,
|
|
+ .status_offset = 0x308,
|
|
+};
|
|
+
|
|
+static const struct jh7110_reset_info jh7110_aon_info = {
|
|
+ .nr_resets = JH7110_AONRST_END,
|
|
+ .assert_offset = 0x38,
|
|
+ .status_offset = 0x3C,
|
|
+};
|
|
+
|
|
+static int jh7110_reset_probe(struct auxiliary_device *adev,
|
|
+ const struct auxiliary_device_id *id)
|
|
+{
|
|
+ struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data);
|
|
+ void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
|
|
+
|
|
+ if (!info || !base)
|
|
+ return -ENODEV;
|
|
+
|
|
+ return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
|
|
+ *base + info->assert_offset,
|
|
+ *base + info->status_offset,
|
|
+ NULL,
|
|
+ info->nr_resets,
|
|
+ NULL);
|
|
+}
|
|
+
|
|
+static const struct auxiliary_device_id jh7110_reset_ids[] = {
|
|
+ {
|
|
+ .name = "clk_starfive_jh7110_sys.rst-sys",
|
|
+ .driver_data = (kernel_ulong_t)&jh7110_sys_info,
|
|
+ },
|
|
+ {
|
|
+ .name = "clk_starfive_jh7110_sys.rst-aon",
|
|
+ .driver_data = (kernel_ulong_t)&jh7110_aon_info,
|
|
+ },
|
|
+ { /* sentinel */ }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids);
|
|
+
|
|
+static struct auxiliary_driver jh7110_reset_driver = {
|
|
+ .probe = jh7110_reset_probe,
|
|
+ .id_table = jh7110_reset_ids,
|
|
+};
|
|
+module_auxiliary_driver(jh7110_reset_driver);
|
|
+
|
|
+MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
|
|
+MODULE_DESCRIPTION("StarFive JH7110 reset driver");
|
|
+MODULE_LICENSE("GPL");
|