mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
93cb81cf2b
https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.96 Manually rebased: generic/hack-6.1/765-mxl-gpy-control-LED-reg-from-DT.patch reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/net/phy/mxl-gpy.c?h=v6.1.96&id=5bd1b7ab6ae5799c136e4319d8644c5ff9c71757 generic: Fix spelling in dmesg output during boot when using the fitblk driver. generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch All other patches automatically rebased. Build system: Kirkwood bcm53xx Signed-off-by: Zxl hhyccc <zxlhhy@gmail.com>
123 lines
3.9 KiB
Diff
123 lines
3.9 KiB
Diff
From 69ed990fda6795039a2b5b37d8ad5df785f4d97b Mon Sep 17 00:00:00 2001
|
|
From: Walker Chen <walker.chen@starfivetech.com>
|
|
Date: Wed, 22 Mar 2023 17:48:18 +0800
|
|
Subject: [PATCH 112/122] dmaengine: dw-axi-dmac: Add support for StarFive
|
|
JH7110 DMA
|
|
|
|
Add DMA reset operation in device probe and use different configuration
|
|
on CH_CFG registers according to match data. Update all uses of
|
|
of_device_is_compatible with of_device_get_match_data.
|
|
|
|
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
|
|
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
|
|
---
|
|
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
|
|
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
|
|
2 files changed, 34 insertions(+), 5 deletions(-)
|
|
|
|
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
|
|
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
|
|
@@ -21,10 +21,12 @@
|
|
#include <linux/kernel.h>
|
|
#include <linux/module.h>
|
|
#include <linux/of.h>
|
|
+#include <linux/of_device.h>
|
|
#include <linux/of_dma.h>
|
|
#include <linux/platform_device.h>
|
|
#include <linux/pm_runtime.h>
|
|
#include <linux/property.h>
|
|
+#include <linux/reset.h>
|
|
#include <linux/slab.h>
|
|
#include <linux/types.h>
|
|
|
|
@@ -46,6 +48,10 @@
|
|
DMA_SLAVE_BUSWIDTH_32_BYTES | \
|
|
DMA_SLAVE_BUSWIDTH_64_BYTES)
|
|
|
|
+#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
|
|
+#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
|
|
+#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
|
|
+
|
|
static inline void
|
|
axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
|
|
{
|
|
@@ -86,7 +92,8 @@ static inline void axi_chan_config_write
|
|
|
|
cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
|
|
config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
|
|
- if (chan->chip->dw->hdata->reg_map_8_channels) {
|
|
+ if (chan->chip->dw->hdata->reg_map_8_channels &&
|
|
+ !chan->chip->dw->hdata->use_cfg2) {
|
|
cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
|
|
config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
|
|
config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
|
|
@@ -1365,11 +1372,12 @@ static int parse_device_properties(struc
|
|
|
|
static int dw_probe(struct platform_device *pdev)
|
|
{
|
|
- struct device_node *node = pdev->dev.of_node;
|
|
struct axi_dma_chip *chip;
|
|
struct resource *mem;
|
|
struct dw_axi_dma *dw;
|
|
struct dw_axi_dma_hcfg *hdata;
|
|
+ struct reset_control *resets;
|
|
+ unsigned int flags;
|
|
u32 i;
|
|
int ret;
|
|
|
|
@@ -1398,12 +1406,25 @@ static int dw_probe(struct platform_devi
|
|
if (IS_ERR(chip->regs))
|
|
return PTR_ERR(chip->regs);
|
|
|
|
- if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
|
|
+ flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
|
|
+ if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
|
|
chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
|
|
if (IS_ERR(chip->apb_regs))
|
|
return PTR_ERR(chip->apb_regs);
|
|
}
|
|
|
|
+ if (flags & AXI_DMA_FLAG_HAS_RESETS) {
|
|
+ resets = devm_reset_control_array_get_exclusive(&pdev->dev);
|
|
+ if (IS_ERR(resets))
|
|
+ return PTR_ERR(resets);
|
|
+
|
|
+ ret = reset_control_deassert(resets);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
|
|
+
|
|
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
|
|
if (IS_ERR(chip->core_clk))
|
|
return PTR_ERR(chip->core_clk);
|
|
@@ -1554,8 +1575,15 @@ static const struct dev_pm_ops dw_axi_dm
|
|
};
|
|
|
|
static const struct of_device_id dw_dma_of_id_table[] = {
|
|
- { .compatible = "snps,axi-dma-1.01a" },
|
|
- { .compatible = "intel,kmb-axi-dma" },
|
|
+ {
|
|
+ .compatible = "snps,axi-dma-1.01a"
|
|
+ }, {
|
|
+ .compatible = "intel,kmb-axi-dma",
|
|
+ .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
|
|
+ }, {
|
|
+ .compatible = "starfive,jh7110-axi-dma",
|
|
+ .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
|
|
+ },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
|
|
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
|
|
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
|
|
@@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
|
|
/* Register map for DMAX_NUM_CHANNELS <= 8 */
|
|
bool reg_map_8_channels;
|
|
bool restrict_axi_burst_len;
|
|
+ bool use_cfg2;
|
|
};
|
|
|
|
struct axi_dma_chan {
|