mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
291 lines
8.3 KiB
Diff
291 lines
8.3 KiB
Diff
From 8daa4c812f3b32a4d56ab48945e552a137fca9b7 Mon Sep 17 00:00:00 2001
|
|
From: Emil Renner Berthing <kernel@esmil.dk>
|
|
Date: Sat, 1 Apr 2023 19:19:17 +0800
|
|
Subject: [PATCH 005/122] clk: starfive: Rename clk-starfive-jh7100.h to
|
|
clk-starfive-jh71x0.h
|
|
|
|
Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making
|
|
the code to be common.
|
|
|
|
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
|
|
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
|
|
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
|
|
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
|
|
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
|
|
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
---
|
|
drivers/clk/starfive/clk-starfive-jh7100-audio.c | 2 +-
|
|
drivers/clk/starfive/clk-starfive-jh7100.c | 2 +-
|
|
drivers/clk/starfive/clk-starfive-jh71x0.c | 2 +-
|
|
.../starfive/{clk-starfive-jh7100.h => clk-starfive-jh71x0.h} | 0
|
|
4 files changed, 3 insertions(+), 3 deletions(-)
|
|
rename drivers/clk/starfive/{clk-starfive-jh7100.h => clk-starfive-jh71x0.h} (100%)
|
|
|
|
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
|
|
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
|
|
@@ -16,7 +16,7 @@
|
|
|
|
#include <dt-bindings/clock/starfive-jh7100-audio.h>
|
|
|
|
-#include "clk-starfive-jh7100.h"
|
|
+#include "clk-starfive-jh71x0.h"
|
|
|
|
/* external clocks */
|
|
#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
|
|
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
|
|
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
|
|
@@ -15,7 +15,7 @@
|
|
|
|
#include <dt-bindings/clock/starfive-jh7100.h>
|
|
|
|
-#include "clk-starfive-jh7100.h"
|
|
+#include "clk-starfive-jh71x0.h"
|
|
|
|
/* external clocks */
|
|
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
|
|
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
|
|
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
|
|
@@ -10,7 +10,7 @@
|
|
#include <linux/device.h>
|
|
#include <linux/io.h>
|
|
|
|
-#include "clk-starfive-jh7100.h"
|
|
+#include "clk-starfive-jh71x0.h"
|
|
|
|
static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
|
|
{
|
|
--- a/drivers/clk/starfive/clk-starfive-jh7100.h
|
|
+++ /dev/null
|
|
@@ -1,114 +0,0 @@
|
|
-/* SPDX-License-Identifier: GPL-2.0 */
|
|
-#ifndef __CLK_STARFIVE_JH7100_H
|
|
-#define __CLK_STARFIVE_JH7100_H
|
|
-
|
|
-#include <linux/bits.h>
|
|
-#include <linux/clk-provider.h>
|
|
-#include <linux/device.h>
|
|
-#include <linux/spinlock.h>
|
|
-
|
|
-/* register fields */
|
|
-#define JH7100_CLK_ENABLE BIT(31)
|
|
-#define JH7100_CLK_INVERT BIT(30)
|
|
-#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
|
|
-#define JH7100_CLK_MUX_SHIFT 24
|
|
-#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
|
|
-#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
|
|
-#define JH7100_CLK_FRAC_SHIFT 8
|
|
-#define JH7100_CLK_INT_MASK GENMASK(7, 0)
|
|
-
|
|
-/* fractional divider min/max */
|
|
-#define JH7100_CLK_FRAC_MIN 100UL
|
|
-#define JH7100_CLK_FRAC_MAX 25599UL
|
|
-
|
|
-/* clock data */
|
|
-struct jh7100_clk_data {
|
|
- const char *name;
|
|
- unsigned long flags;
|
|
- u32 max;
|
|
- u8 parents[4];
|
|
-};
|
|
-
|
|
-#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = CLK_SET_RATE_PARENT | (_flags), \
|
|
- .max = JH7100_CLK_ENABLE, \
|
|
- .parents = { [0] = _parent }, \
|
|
-}
|
|
-
|
|
-#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = 0, \
|
|
- .max = _max, \
|
|
- .parents = { [0] = _parent }, \
|
|
-}
|
|
-
|
|
-#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = _flags, \
|
|
- .max = JH7100_CLK_ENABLE | (_max), \
|
|
- .parents = { [0] = _parent }, \
|
|
-}
|
|
-
|
|
-#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = 0, \
|
|
- .max = JH7100_CLK_FRAC_MAX, \
|
|
- .parents = { [0] = _parent }, \
|
|
-}
|
|
-
|
|
-#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = 0, \
|
|
- .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
|
|
- .parents = { __VA_ARGS__ }, \
|
|
-}
|
|
-
|
|
-#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = _flags, \
|
|
- .max = JH7100_CLK_ENABLE | \
|
|
- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
|
|
- .parents = { __VA_ARGS__ }, \
|
|
-}
|
|
-
|
|
-#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = 0, \
|
|
- .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
|
|
- .parents = { __VA_ARGS__ }, \
|
|
-}
|
|
-
|
|
-#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = _flags, \
|
|
- .max = JH7100_CLK_ENABLE | \
|
|
- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
|
|
- .parents = { __VA_ARGS__ }, \
|
|
-}
|
|
-
|
|
-#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
|
|
- .name = _name, \
|
|
- .flags = CLK_SET_RATE_PARENT, \
|
|
- .max = JH7100_CLK_INVERT, \
|
|
- .parents = { [0] = _parent }, \
|
|
-}
|
|
-
|
|
-struct jh7100_clk {
|
|
- struct clk_hw hw;
|
|
- unsigned int idx;
|
|
- unsigned int max_div;
|
|
-};
|
|
-
|
|
-struct jh7100_clk_priv {
|
|
- /* protect clk enable and set rate/parent from happening at the same time */
|
|
- spinlock_t rmw_lock;
|
|
- struct device *dev;
|
|
- void __iomem *base;
|
|
- struct clk_hw *pll[3];
|
|
- struct jh7100_clk reg[];
|
|
-};
|
|
-
|
|
-const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
|
|
-
|
|
-#endif
|
|
--- /dev/null
|
|
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
|
|
@@ -0,0 +1,114 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0 */
|
|
+#ifndef __CLK_STARFIVE_JH7100_H
|
|
+#define __CLK_STARFIVE_JH7100_H
|
|
+
|
|
+#include <linux/bits.h>
|
|
+#include <linux/clk-provider.h>
|
|
+#include <linux/device.h>
|
|
+#include <linux/spinlock.h>
|
|
+
|
|
+/* register fields */
|
|
+#define JH7100_CLK_ENABLE BIT(31)
|
|
+#define JH7100_CLK_INVERT BIT(30)
|
|
+#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
|
|
+#define JH7100_CLK_MUX_SHIFT 24
|
|
+#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
|
|
+#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
|
|
+#define JH7100_CLK_FRAC_SHIFT 8
|
|
+#define JH7100_CLK_INT_MASK GENMASK(7, 0)
|
|
+
|
|
+/* fractional divider min/max */
|
|
+#define JH7100_CLK_FRAC_MIN 100UL
|
|
+#define JH7100_CLK_FRAC_MAX 25599UL
|
|
+
|
|
+/* clock data */
|
|
+struct jh7100_clk_data {
|
|
+ const char *name;
|
|
+ unsigned long flags;
|
|
+ u32 max;
|
|
+ u8 parents[4];
|
|
+};
|
|
+
|
|
+#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = CLK_SET_RATE_PARENT | (_flags), \
|
|
+ .max = JH7100_CLK_ENABLE, \
|
|
+ .parents = { [0] = _parent }, \
|
|
+}
|
|
+
|
|
+#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = 0, \
|
|
+ .max = _max, \
|
|
+ .parents = { [0] = _parent }, \
|
|
+}
|
|
+
|
|
+#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = _flags, \
|
|
+ .max = JH7100_CLK_ENABLE | (_max), \
|
|
+ .parents = { [0] = _parent }, \
|
|
+}
|
|
+
|
|
+#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = 0, \
|
|
+ .max = JH7100_CLK_FRAC_MAX, \
|
|
+ .parents = { [0] = _parent }, \
|
|
+}
|
|
+
|
|
+#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = 0, \
|
|
+ .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
|
|
+ .parents = { __VA_ARGS__ }, \
|
|
+}
|
|
+
|
|
+#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = _flags, \
|
|
+ .max = JH7100_CLK_ENABLE | \
|
|
+ (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
|
|
+ .parents = { __VA_ARGS__ }, \
|
|
+}
|
|
+
|
|
+#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = 0, \
|
|
+ .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
|
|
+ .parents = { __VA_ARGS__ }, \
|
|
+}
|
|
+
|
|
+#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = _flags, \
|
|
+ .max = JH7100_CLK_ENABLE | \
|
|
+ (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
|
|
+ .parents = { __VA_ARGS__ }, \
|
|
+}
|
|
+
|
|
+#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
|
|
+ .name = _name, \
|
|
+ .flags = CLK_SET_RATE_PARENT, \
|
|
+ .max = JH7100_CLK_INVERT, \
|
|
+ .parents = { [0] = _parent }, \
|
|
+}
|
|
+
|
|
+struct jh7100_clk {
|
|
+ struct clk_hw hw;
|
|
+ unsigned int idx;
|
|
+ unsigned int max_div;
|
|
+};
|
|
+
|
|
+struct jh7100_clk_priv {
|
|
+ /* protect clk enable and set rate/parent from happening at the same time */
|
|
+ spinlock_t rmw_lock;
|
|
+ struct device *dev;
|
|
+ void __iomem *base;
|
|
+ struct clk_hw *pll[3];
|
|
+ struct jh7100_clk reg[];
|
|
+};
|
|
+
|
|
+const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
|
|
+
|
|
+#endif
|