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229 lines
6.9 KiB
Diff
229 lines
6.9 KiB
Diff
From 8f5722ac3e42a33345bfd82b7ad6a153134a4239 Mon Sep 17 00:00:00 2001
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From: Jonas Pfeil <pfeiljonas@gmx.de>
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Date: Tue, 8 Nov 2016 00:18:39 +0100
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Subject: [PATCH] drm/vc4: Add fragment shader threading support
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FS threading brings performance improvements of 0-20% in glmark2.
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The validation code checks for thread switch signals and ensures that
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the registers of the other thread are not touched, and that our clamps
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are not live across thread switches. It also checks that the
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threading and branching instructions do not interfere.
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(Original patch by Jonas, changes by anholt for style cleanup,
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removing validation the kernel doesn't need to do, and adding the flag
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for userspace).
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v2: Minor style fixes from checkpatch.
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Signed-off-by: Jonas Pfeil <pfeiljonas@gmx.de>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit c778cc5df944291dcdb1ca7a6bb781fbc22550c5)
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---
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drivers/gpu/drm/vc4/vc4_drv.c | 1 +
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drivers/gpu/drm/vc4/vc4_drv.h | 2 +
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drivers/gpu/drm/vc4/vc4_validate.c | 17 +++++---
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drivers/gpu/drm/vc4/vc4_validate_shaders.c | 63 ++++++++++++++++++++++++++++++
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include/uapi/drm/vc4_drm.h | 1 +
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5 files changed, 79 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_drv.c
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+++ b/drivers/gpu/drm/vc4/vc4_drv.c
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@@ -82,6 +82,7 @@ static int vc4_get_param_ioctl(struct dr
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break;
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case DRM_VC4_PARAM_SUPPORTS_BRANCHES:
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case DRM_VC4_PARAM_SUPPORTS_ETC1:
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+ case DRM_VC4_PARAM_SUPPORTS_THREADED_FS:
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args->value = true;
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break;
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default:
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -385,6 +385,8 @@ struct vc4_validated_shader_info {
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uint32_t num_uniform_addr_offsets;
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uint32_t *uniform_addr_offsets;
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+
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+ bool is_threaded;
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};
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/**
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--- a/drivers/gpu/drm/vc4/vc4_validate.c
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+++ b/drivers/gpu/drm/vc4/vc4_validate.c
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@@ -789,11 +789,6 @@ validate_gl_shader_rec(struct drm_device
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exec->shader_rec_v += roundup(packet_size, 16);
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exec->shader_rec_size -= packet_size;
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- if (!(*(uint16_t *)pkt_u & VC4_SHADER_FLAG_FS_SINGLE_THREAD)) {
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- DRM_ERROR("Multi-threaded fragment shaders not supported.\n");
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- return -EINVAL;
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- }
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-
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for (i = 0; i < shader_reloc_count; i++) {
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if (src_handles[i] > exec->bo_count) {
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DRM_ERROR("Shader handle %d too big\n", src_handles[i]);
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@@ -810,6 +805,18 @@ validate_gl_shader_rec(struct drm_device
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return -EINVAL;
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}
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+ if (((*(uint16_t *)pkt_u & VC4_SHADER_FLAG_FS_SINGLE_THREAD) == 0) !=
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+ to_vc4_bo(&bo[0]->base)->validated_shader->is_threaded) {
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+ DRM_ERROR("Thread mode of CL and FS do not match\n");
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+ return -EINVAL;
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+ }
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+
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+ if (to_vc4_bo(&bo[1]->base)->validated_shader->is_threaded ||
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+ to_vc4_bo(&bo[2]->base)->validated_shader->is_threaded) {
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+ DRM_ERROR("cs and vs cannot be threaded\n");
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+ return -EINVAL;
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+ }
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+
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for (i = 0; i < shader_reloc_count; i++) {
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struct vc4_validated_shader_info *validated_shader;
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uint32_t o = shader_reloc_offsets[i];
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--- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
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+++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
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@@ -83,6 +83,13 @@ struct vc4_shader_validation_state {
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* basic blocks.
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*/
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bool needs_uniform_address_for_loop;
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+
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+ /* Set when we find an instruction writing the top half of the
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+ * register files. If we allowed writing the unusable regs in
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+ * a threaded shader, then the other shader running on our
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+ * QPU's clamp validation would be invalid.
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+ */
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+ bool all_registers_used;
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};
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static uint32_t
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@@ -119,6 +126,13 @@ raddr_add_a_to_live_reg_index(uint64_t i
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}
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static bool
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+live_reg_is_upper_half(uint32_t lri)
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+{
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+ return (lri >= 16 && lri < 32) ||
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+ (lri >= 32 + 16 && lri < 32 + 32);
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+}
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+
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+static bool
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is_tmu_submit(uint32_t waddr)
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{
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return (waddr == QPU_W_TMU0_S ||
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@@ -390,6 +404,9 @@ check_reg_write(struct vc4_validated_sha
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} else {
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validation_state->live_immediates[lri] = ~0;
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}
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+
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+ if (live_reg_is_upper_half(lri))
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+ validation_state->all_registers_used = true;
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}
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switch (waddr) {
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@@ -598,6 +615,11 @@ check_instruction_reads(struct vc4_valid
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}
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}
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+ if ((raddr_a >= 16 && raddr_a < 32) ||
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+ (raddr_b >= 16 && raddr_b < 32 && sig != QPU_SIG_SMALL_IMM)) {
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+ validation_state->all_registers_used = true;
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+ }
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+
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return true;
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}
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@@ -753,6 +775,7 @@ vc4_validate_shader(struct drm_gem_cma_o
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{
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bool found_shader_end = false;
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int shader_end_ip = 0;
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+ uint32_t last_thread_switch_ip = -3;
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uint32_t ip;
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struct vc4_validated_shader_info *validated_shader = NULL;
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struct vc4_shader_validation_state validation_state;
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@@ -785,6 +808,17 @@ vc4_validate_shader(struct drm_gem_cma_o
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if (!vc4_handle_branch_target(&validation_state))
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goto fail;
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+ if (ip == last_thread_switch_ip + 3) {
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+ /* Reset r0-r3 live clamp data */
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+ int i;
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+
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+ for (i = 64; i < LIVE_REG_COUNT; i++) {
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+ validation_state.live_min_clamp_offsets[i] = ~0;
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+ validation_state.live_max_clamp_regs[i] = false;
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+ validation_state.live_immediates[i] = ~0;
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+ }
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+ }
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+
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switch (sig) {
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case QPU_SIG_NONE:
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case QPU_SIG_WAIT_FOR_SCOREBOARD:
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@@ -794,6 +828,8 @@ vc4_validate_shader(struct drm_gem_cma_o
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case QPU_SIG_LOAD_TMU1:
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case QPU_SIG_PROG_END:
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case QPU_SIG_SMALL_IMM:
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+ case QPU_SIG_THREAD_SWITCH:
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+ case QPU_SIG_LAST_THREAD_SWITCH:
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if (!check_instruction_writes(validated_shader,
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&validation_state)) {
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DRM_ERROR("Bad write at ip %d\n", ip);
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@@ -809,6 +845,18 @@ vc4_validate_shader(struct drm_gem_cma_o
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shader_end_ip = ip;
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}
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+ if (sig == QPU_SIG_THREAD_SWITCH ||
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+ sig == QPU_SIG_LAST_THREAD_SWITCH) {
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+ validated_shader->is_threaded = true;
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+
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+ if (ip < last_thread_switch_ip + 3) {
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+ DRM_ERROR("Thread switch too soon after "
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+ "last switch at ip %d\n", ip);
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+ goto fail;
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+ }
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+ last_thread_switch_ip = ip;
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+ }
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+
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break;
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case QPU_SIG_LOAD_IMM:
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@@ -823,6 +871,13 @@ vc4_validate_shader(struct drm_gem_cma_o
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if (!check_branch(inst, validated_shader,
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&validation_state, ip))
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goto fail;
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+
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+ if (ip < last_thread_switch_ip + 3) {
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+ DRM_ERROR("Branch in thread switch at ip %d",
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+ ip);
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+ goto fail;
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+ }
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+
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break;
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default:
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DRM_ERROR("Unsupported QPU signal %d at "
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@@ -844,6 +899,14 @@ vc4_validate_shader(struct drm_gem_cma_o
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goto fail;
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}
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+ /* Might corrupt other thread */
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+ if (validated_shader->is_threaded &&
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+ validation_state.all_registers_used) {
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+ DRM_ERROR("Shader uses threading, but uses the upper "
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+ "half of the registers, too\n");
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+ goto fail;
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+ }
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+
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/* If we did a backwards branch and we haven't emitted a uniforms
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* reset since then, we still need the uniforms stream to have the
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* uniforms address available so that the backwards branch can do its
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--- a/include/uapi/drm/vc4_drm.h
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+++ b/include/uapi/drm/vc4_drm.h
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@@ -287,6 +287,7 @@ struct drm_vc4_get_hang_state {
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#define DRM_VC4_PARAM_V3D_IDENT2 2
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#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
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#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
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+#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
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struct drm_vc4_get_param {
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__u32 param;
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