mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
67 lines
2.0 KiB
Diff
67 lines
2.0 KiB
Diff
From 61959c53020fff0584d88e28d6dae9806184f1a8 Mon Sep 17 00:00:00 2001
|
|
From: Minghuan Lian <Minghuan.Lian@nxp.com>
|
|
Date: Mon, 29 Feb 2016 17:24:15 -0600
|
|
Subject: [PATCH 50/70] PCI: layerscape: Fix MSG TLP drop setting
|
|
|
|
Some kinds of Layerscape PCIe controllers will forward the received message
|
|
TLPs to system application address space, which could corrupt system memory
|
|
or lead to a system hang. Enable MSG_DROP to fix this issue.
|
|
|
|
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
|
|
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
|
---
|
|
drivers/pci/host/pci-layerscape.c | 21 +++++++++++++--------
|
|
1 file changed, 13 insertions(+), 8 deletions(-)
|
|
|
|
--- a/drivers/pci/host/pci-layerscape.c
|
|
+++ b/drivers/pci/host/pci-layerscape.c
|
|
@@ -77,6 +77,16 @@ static void ls_pcie_fix_class(struct ls_
|
|
iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
|
|
}
|
|
|
|
+/* Drop MSG TLP except for Vendor MSG */
|
|
+static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
|
|
+{
|
|
+ u32 val;
|
|
+
|
|
+ val = ioread32(pcie->dbi + PCIE_STRFMR1);
|
|
+ val &= 0xDFFFFFFF;
|
|
+ iowrite32(val, pcie->dbi + PCIE_STRFMR1);
|
|
+}
|
|
+
|
|
static int ls1021_pcie_link_up(struct pcie_port *pp)
|
|
{
|
|
u32 state;
|
|
@@ -97,7 +107,7 @@ static int ls1021_pcie_link_up(struct pc
|
|
static void ls1021_pcie_host_init(struct pcie_port *pp)
|
|
{
|
|
struct ls_pcie *pcie = to_ls_pcie(pp);
|
|
- u32 val, index[2];
|
|
+ u32 index[2];
|
|
|
|
pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
|
|
"fsl,pcie-scfg");
|
|
@@ -116,13 +126,7 @@ static void ls1021_pcie_host_init(struct
|
|
|
|
dw_pcie_setup_rc(pp);
|
|
|
|
- /*
|
|
- * LS1021A Workaround for internal TKT228622
|
|
- * to fix the INTx hang issue
|
|
- */
|
|
- val = ioread32(pcie->dbi + PCIE_STRFMR1);
|
|
- val &= 0xffff;
|
|
- iowrite32(val, pcie->dbi + PCIE_STRFMR1);
|
|
+ ls_pcie_drop_msg_tlp(pcie);
|
|
}
|
|
|
|
static int ls_pcie_link_up(struct pcie_port *pp)
|
|
@@ -147,6 +151,7 @@ static void ls_pcie_host_init(struct pci
|
|
iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
|
|
ls_pcie_fix_class(pcie);
|
|
ls_pcie_clear_multifunction(pcie);
|
|
+ ls_pcie_drop_msg_tlp(pcie);
|
|
iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
|
|
}
|
|
|