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49 lines
2.1 KiB
Diff
49 lines
2.1 KiB
Diff
From 21261e30679118b96ed537d1cdf9e12682fc1b29 Mon Sep 17 00:00:00 2001
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From: Eugen Hristev <eugen.hristev@microchip.com>
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Date: Wed, 9 Jun 2021 15:00:28 +0200
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Subject: [PATCH 193/247] media: atmel: atmel-sama5d2-isc: fix YUYV format
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SAMA5D2 does not have the YCYC field for the RLP (rounding, limiting,
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packaging) module.
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The YCYC field is supposed to work with interleaved YUV formats like YUYV.
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In SAMA5D2, we have to use YYCC field, which is used for both planar
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formats like YUV420 and interleaved formats like YUYV.
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Fix the according rlp callback to replace the generic YCYC field (which
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makes more sense from a logical point of view) with the required YYCC
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field.
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Fixes: debfa496871c ("media: atmel: atmel-isc-base: add support for more formats and additional pipeline modules")
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Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
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Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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---
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.../media/platform/atmel/atmel-sama5d2-isc.c | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
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+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
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@@ -255,6 +255,23 @@ static void isc_sama5d2_config_rlp(struc
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struct regmap *regmap = isc->regmap;
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u32 rlp_mode = isc->config.rlp_cfg_mode;
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+ /*
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+ * In sama5d2, the YUV planar modes and the YUYV modes are treated
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+ * in the same way in RLP register.
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+ * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n)
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+ * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n)
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+ * but in sama5d2, the YCYC mode does not exist, and YYCC must be
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+ * selected for both planar and interleaved modes, as in fact
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+ * both modes are supported.
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+ *
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+ * Thus, if the YCYC mode is selected, replace it with the
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+ * sama5d2-compliant mode which is YYCC .
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+ */
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+ if ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) {
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+ rlp_mode &= ~ISC_RLP_CFG_MODE_MASK;
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+ rlp_mode |= ISC_RLP_CFG_MODE_YYCC;
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+ }
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+
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regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
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ISC_RLP_CFG_MODE_MASK, rlp_mode);
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}
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