mirror of
https://github.com/openwrt/openwrt.git
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a105eac4dd
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
298 lines
10 KiB
Diff
298 lines
10 KiB
Diff
From 21bdcd324f769545b1765fe391d939a1edd07cbb Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 20 Jan 2016 09:55:08 +0100
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Subject: [PATCH 039/102] soc: mediatek: PMIC wrap: add a slave specific
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struct
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This patch adds a new struct pwrap_slv_type that we use to store the slave
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specific data. The patch adds 2 new helper functions to access the dew
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registers. The slave type is looked up via the wrappers child node.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/soc/mediatek/mtk-pmic-wrap.c | 159 ++++++++++++++++++++++++----------
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1 file changed, 112 insertions(+), 47 deletions(-)
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--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
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+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
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@@ -69,33 +69,54 @@
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PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
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PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
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-/* macro for slave device wrapper registers */
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-#define PWRAP_DEW_BASE 0xbc00
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-#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
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-#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
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-#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
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-#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
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-#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
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-#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
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-#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
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-#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
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-#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
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-#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
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-#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
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-#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
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-#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
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-#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
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-#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
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-#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
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-#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
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-#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
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-#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
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-#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
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-#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
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-#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
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-#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
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-#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
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-#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
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+/* defines for slave device wrapper registers */
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+enum dew_regs {
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+ PWRAP_DEW_BASE,
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+ PWRAP_DEW_DIO_EN,
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+ PWRAP_DEW_READ_TEST,
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+ PWRAP_DEW_WRITE_TEST,
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+ PWRAP_DEW_CRC_EN,
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+ PWRAP_DEW_CRC_VAL,
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+ PWRAP_DEW_MON_GRP_SEL,
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+ PWRAP_DEW_CIPHER_KEY_SEL,
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+ PWRAP_DEW_CIPHER_IV_SEL,
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+ PWRAP_DEW_CIPHER_RDY,
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+ PWRAP_DEW_CIPHER_MODE,
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+ PWRAP_DEW_CIPHER_SWRST,
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+
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+ /* MT6397 only regs */
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+ PWRAP_DEW_EVENT_OUT_EN,
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+ PWRAP_DEW_EVENT_SRC_EN,
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+ PWRAP_DEW_EVENT_SRC,
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+ PWRAP_DEW_EVENT_FLAG,
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+ PWRAP_DEW_MON_FLAG_SEL,
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+ PWRAP_DEW_EVENT_TEST,
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+ PWRAP_DEW_CIPHER_LOAD,
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+ PWRAP_DEW_CIPHER_START,
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+};
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+
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+static const u32 mt6397_regs[] = {
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+ [PWRAP_DEW_BASE] = 0xbc00,
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+ [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
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+ [PWRAP_DEW_DIO_EN] = 0xbc02,
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+ [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
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+ [PWRAP_DEW_EVENT_SRC] = 0xbc06,
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+ [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
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+ [PWRAP_DEW_READ_TEST] = 0xbc0a,
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+ [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
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+ [PWRAP_DEW_CRC_EN] = 0xbc0e,
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+ [PWRAP_DEW_CRC_VAL] = 0xbc10,
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+ [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
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+ [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
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+ [PWRAP_DEW_EVENT_TEST] = 0xbc16,
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+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
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+ [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
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+ [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
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+ [PWRAP_DEW_CIPHER_START] = 0xbc1e,
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+ [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
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+ [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
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+ [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
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+};
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enum pwrap_regs {
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PWRAP_MUX_SEL,
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@@ -349,16 +370,26 @@ static int mt8135_regs[] = {
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[PWRAP_DCM_DBC_PRD] = 0x160,
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};
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+enum pmic_type {
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+ PMIC_MT6397,
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+};
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+
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enum pwrap_type {
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PWRAP_MT8135,
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PWRAP_MT8173,
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};
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+struct pwrap_slv_type {
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+ const u32 *dew_regs;
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+ enum pmic_type type;
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+};
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+
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struct pmic_wrapper {
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struct device *dev;
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void __iomem *base;
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struct regmap *regmap;
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const struct pmic_wrapper_type *master;
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+ const struct pwrap_slv_type *slave;
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struct clk *clk_spi;
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struct clk *clk_wrap;
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struct reset_control *rstc;
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@@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_
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for (i = 0; i < 4; i++) {
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pwrap_writel(wrp, i, PWRAP_SIDLY);
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- pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
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+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
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+ &rdata);
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if (rdata == PWRAP_DEW_READ_TEST_VAL) {
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dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
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pass |= 1 << i;
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@@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(s
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u32 rdata;
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int ret;
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- ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
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+ ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
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+ &rdata);
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if (ret)
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return 0;
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@@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic
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}
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/* Config cipher mode @PMIC */
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- pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
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- pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
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- pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
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- pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
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- pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
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- pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
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/* wait for cipher data ready@AP */
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ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
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@@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic
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}
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/* wait for cipher mode idle */
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- pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
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ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
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if (ret) {
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dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
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@@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic
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pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
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/* Write Test */
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- if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
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- pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
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- (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
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+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
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+ PWRAP_DEW_WRITE_TEST_VAL) ||
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+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
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+ &rdata) ||
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+ (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
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dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
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return -EFAULT;
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}
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@@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specifi
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writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
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/* enable PMIC event out and sources */
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- if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
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- pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
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+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
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+ 0x1) ||
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
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+ 0xffff)) {
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dev_err(wrp->dev, "enable dewrap fail\n");
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return -EFAULT;
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}
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@@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specifi
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static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
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{
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/* PMIC_DEWRAP enables */
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- if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
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- pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
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+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
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+ 0x1) ||
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
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+ 0xffff)) {
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dev_err(wrp->dev, "enable dewrap fail\n");
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return -EFAULT;
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}
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@@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrappe
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return ret;
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/* Enable dual IO mode */
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- pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
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/* Check IDLE & INIT_DONE in advance */
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ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
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@@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrappe
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pwrap_writel(wrp, 1, PWRAP_DIO_EN);
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/* Read Test */
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- pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
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+ pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
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if (rdata != PWRAP_DEW_READ_TEST_VAL) {
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dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
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PWRAP_DEW_READ_TEST_VAL, rdata);
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@@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrappe
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return ret;
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/* Signature checking - using CRC */
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- if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
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+ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
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return -EFAULT;
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pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
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pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
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- pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
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+ pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
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+ PWRAP_SIG_ADR);
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pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
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if (wrp->master->type == PWRAP_MT8135)
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@@ -818,6 +858,21 @@ static const struct regmap_config pwrap_
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.max_register = 0xffff,
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};
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+static const struct pwrap_slv_type pmic_mt6397 = {
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+ .dew_regs = mt6397_regs,
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+ .type = PMIC_MT6397,
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+};
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+
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+static const struct of_device_id of_slave_match_tbl[] = {
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+ {
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+ .compatible = "mediatek,mt6397",
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+ .data = &pmic_mt6397,
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+ }, {
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+ /* sentinel */
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+ }
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+};
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+MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
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+
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static struct pmic_wrapper_type pwrap_mt8135 = {
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.regs = mt8135_regs,
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.type = PWRAP_MT8135,
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@@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_d
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struct device_node *np = pdev->dev.of_node;
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const struct of_device_id *of_id =
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of_match_device(of_pwrap_match_tbl, &pdev->dev);
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+ const struct of_device_id *of_slave_id = NULL;
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struct resource *res;
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+ if (pdev->dev.of_node->child)
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+ of_slave_id = of_match_node(of_slave_match_tbl,
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+ pdev->dev.of_node->child);
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+ if (!of_slave_id) {
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+ dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
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+ return -EINVAL;
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+ }
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+
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wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
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if (!wrp)
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return -ENOMEM;
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@@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_d
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platform_set_drvdata(pdev, wrp);
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wrp->master = of_id->data;
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+ wrp->slave = of_slave_id->data;
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wrp->dev = &pdev->dev;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
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